Simulation Results: pattgen

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.98 %
  • code
  • 98.87 %
  • assert
  • 96.65 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 2.000s 35.116us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 12.896us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 13.074us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 2.000s 103.038us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 61.040us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 54.722us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 13.074us 1 1 100.00
pattgen_csr_aliasing 1.000s 61.040us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 126.000s 45590.360us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 10.000s 2541.741us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 101.953us 1 1 100.00
stress_all 1 1 100.00
pattgen_stress_all 2.000s 40.755us 1 1 100.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 30.551us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 23.865us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 20.774us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 20.774us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 12.896us 1 1 100.00
pattgen_csr_rw 1.000s 13.074us 1 1 100.00
pattgen_csr_aliasing 1.000s 61.040us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 151.633us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 12.896us 1 1 100.00
pattgen_csr_rw 1.000s 13.074us 1 1 100.00
pattgen_csr_aliasing 1.000s 61.040us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 151.633us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_tl_intg_err 1.000s 50.979us 1 1 100.00
pattgen_sec_cm 1.000s 66.547us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 1.000s 50.979us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 12.000s 4151.677us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 2.000s 26.568us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
pattgen_stress_all_with_rand_reset 62459932816083195319062676385429604990094282033113832466772715782456355124273 259
UVM_ERROR @ 2297325256 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2297325256 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 5/10
UVM_INFO @ 2297471087 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]