Simulation Results: pwrmgr

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.04 %
  • code
  • 94.58 %
  • assert
  • 96.34 %
  • func
  • 97.20 %
  • line
  • 98.92 %
  • branch
  • 95.61 %
  • cond
  • 94.34 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.640s 26.250us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.780s 44.083us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.700s 20.729us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.090s 137.168us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.140s 385.511us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.930s 99.441us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.700s 20.729us 1 1 100.00
pwrmgr_csr_aliasing 1.140s 385.511us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.660s 96.711us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.660s 96.711us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.860s 138.776us 1 1 100.00
pwrmgr_lowpower_invalid 0.750s 62.283us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.850s 64.141us 1 1 100.00
pwrmgr_reset_invalid 1.180s 91.371us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.850s 64.141us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 1.000s 304.756us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 1.070s 268.823us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.650s 31.495us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.670s 518.016us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.660s 29.728us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.420s 912.698us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.420s 912.698us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.780s 44.083us 1 1 100.00
pwrmgr_csr_rw 0.700s 20.729us 1 1 100.00
pwrmgr_csr_aliasing 1.140s 385.511us 1 1 100.00
pwrmgr_same_csr_outstanding 0.830s 35.747us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.780s 44.083us 1 1 100.00
pwrmgr_csr_rw 0.700s 20.729us 1 1 100.00
pwrmgr_csr_aliasing 1.140s 385.511us 1 1 100.00
pwrmgr_same_csr_outstanding 0.830s 35.747us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 0.730s 15.642us 0 1 0.00
pwrmgr_sec_cm 0.670s 8.021us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.670s 8.021us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.670s 8.021us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.730s 15.642us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.600s 1056.242us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 1.000s 304.756us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.780s 78.344us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.610s 31.167us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.670s 8.021us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.670s 8.021us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.670s 8.021us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.700s 88.454us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.740s 36.922us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.030s 204.639us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.700s 20.729us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.700s 20.729us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.970s 107.443us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 8.060s 8664.517us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire
pwrmgr_tl_intg_err 84441031524681406193946107518030036547538445025735475484907371879882964720000 85
UVM_INFO @ 15641833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 62011838396440477638567058765413342195122378167219602559741137790330186814019 77
UVM_INFO @ 8020567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---