Simulation Results: rom_ctrl/32kb

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.24 %
  • code
  • 97.79 %
  • assert
  • 96.80 %
  • func
  • 97.14 %
  • line
  • 99.46 %
  • branch
  • 98.91 %
  • cond
  • 97.47 %
  • toggle
  • 99.80 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.280s 333.120us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.310s 136.896us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.200s 384.333us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.660s 292.855us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.520s 131.513us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.130s 194.924us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.200s 384.333us 1 1 100.00
rom_ctrl_csr_aliasing 3.520s 131.513us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.120s 539.818us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.530s 170.063us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 5.480s 184.203us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 10.960s 464.456us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 5.920s 712.639us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.570s 500.179us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.680s 127.164us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.680s 127.164us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.310s 136.896us 1 1 100.00
rom_ctrl_csr_rw 3.200s 384.333us 1 1 100.00
rom_ctrl_csr_aliasing 3.520s 131.513us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.360s 384.586us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.310s 136.896us 1 1 100.00
rom_ctrl_csr_rw 3.200s 384.333us 1 1 100.00
rom_ctrl_csr_aliasing 3.520s 131.513us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.360s 384.586us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 85.680s 2975.675us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 19.900s 1631.187us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 100.410s 629.437us 1 1 100.00
rom_ctrl_tl_intg_err 22.650s 667.161us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 100.410s 629.437us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 100.410s 629.437us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 85.680s 2975.675us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 85.680s 2975.675us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 85.680s 2975.675us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 85.680s 2975.675us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 85.680s 2975.675us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 100.410s 629.437us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 100.410s 629.437us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.280s 333.120us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.280s 333.120us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.280s 333.120us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 22.650s 667.161us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 85.680s 2975.675us 1 1 100.00
rom_ctrl_kmac_err_chk 5.920s 712.639us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 85.680s 2975.675us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 85.680s 2975.675us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 85.680s 2975.675us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 19.900s 1631.187us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 100.410s 629.437us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 85.640s 1230.561us 1 1 100.00