Simulation Results: rom_ctrl/64kb

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.45 %
  • code
  • 99.14 %
  • assert
  • 96.80 %
  • func
  • 96.42 %
  • line
  • 99.59 %
  • branch
  • 99.27 %
  • cond
  • 97.62 %
  • toggle
  • 99.21 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.770s 219.941us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 9.970s 1124.511us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.750s 1010.327us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.990s 289.459us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.470s 1061.709us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.500s 580.139us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.750s 1010.327us 1 1 100.00
rom_ctrl_csr_aliasing 6.470s 1061.709us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.160s 215.138us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.510s 699.828us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 9.110s 1099.710us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 22.060s 5102.906us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.470s 1807.437us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.150s 287.893us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.800s 1871.901us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.800s 1871.901us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.970s 1124.511us 1 1 100.00
rom_ctrl_csr_rw 5.750s 1010.327us 1 1 100.00
rom_ctrl_csr_aliasing 6.470s 1061.709us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.240s 298.671us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.970s 1124.511us 1 1 100.00
rom_ctrl_csr_rw 5.750s 1010.327us 1 1 100.00
rom_ctrl_csr_aliasing 6.470s 1061.709us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.240s 298.671us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.730s 2239.798us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.120s 3029.917us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 231.100s 540.052us 1 1 100.00
rom_ctrl_tl_intg_err 52.180s 314.635us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 231.100s 540.052us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 231.100s 540.052us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.730s 2239.798us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.730s 2239.798us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.730s 2239.798us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.730s 2239.798us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.730s 2239.798us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 231.100s 540.052us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 231.100s 540.052us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.770s 219.941us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.770s 219.941us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.770s 219.941us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 52.180s 314.635us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.730s 2239.798us 1 1 100.00
rom_ctrl_kmac_err_chk 14.470s 1807.437us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.730s 2239.798us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.730s 2239.798us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 102.730s 2239.798us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.120s 3029.917us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 231.100s 540.052us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 74.130s 8252.870us 1 1 100.00