Simulation Results: rstmgr

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.29 %
  • code
  • 99.25 %
  • assert
  • 97.86 %
  • func
  • 97.76 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.40 %
  • toggle
  • 99.25 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.230s 126.369us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.930s 144.820us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.880s 64.443us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.640s 274.205us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.980s 449.452us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.030s 119.072us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.880s 64.443us 1 1 100.00
rstmgr_csr_aliasing 1.980s 449.452us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.950s 131.740us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.650s 153.824us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.110s 214.244us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.160s 1096.674us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.160s 1096.674us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.160s 1096.674us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.160s 1096.674us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 22.250s 9421.438us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.970s 77.452us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.010s 363.654us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.010s 363.654us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.930s 144.820us 1 1 100.00
rstmgr_csr_rw 0.880s 64.443us 1 1 100.00
rstmgr_csr_aliasing 1.980s 449.452us 1 1 100.00
rstmgr_same_csr_outstanding 0.970s 109.778us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.930s 144.820us 1 1 100.00
rstmgr_csr_rw 0.880s 64.443us 1 1 100.00
rstmgr_csr_aliasing 1.980s 449.452us 1 1 100.00
rstmgr_same_csr_outstanding 0.970s 109.778us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 10.350s 8502.800us 1 1 100.00
rstmgr_tl_intg_err 2.610s 1071.576us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 10.350s 8502.800us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 10.350s 8502.800us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.610s 1071.576us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.980s 110.531us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 5.680s 1964.296us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.160s 302.537us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 10.350s 8502.800us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.880s 64.443us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.880s 64.443us 1 1 100.00