Simulation Results: rv_timer

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.37 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 95.29 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.670s 45.089us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.610s 73.414us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.620s 24.220us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.360s 64.727us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 131.764us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.720s 54.270us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.620s 24.220us 1 1 100.00
rv_timer_csr_aliasing 1.000s 131.764us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.010s 204.002us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.280s 3822.994us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 391.590s 387677.345us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 391.590s 387677.345us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.980s 5397.519us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.600s 32.548us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.650s 41.601us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.400s 200.011us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.400s 200.011us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.610s 73.414us 1 1 100.00
rv_timer_csr_rw 0.620s 24.220us 1 1 100.00
rv_timer_csr_aliasing 1.000s 131.764us 1 1 100.00
rv_timer_same_csr_outstanding 0.720s 82.235us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.610s 73.414us 1 1 100.00
rv_timer_csr_rw 0.620s 24.220us 1 1 100.00
rv_timer_csr_aliasing 1.000s 131.764us 1 1 100.00
rv_timer_same_csr_outstanding 0.720s 82.235us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.820s 122.438us 1 1 100.00
rv_timer_tl_intg_err 1.190s 366.357us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.190s 366.357us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.910s 323.207us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 1.010s 778.082us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 36.310s 4662.115us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 20413514035071079742616796034585993102791238024560939109631255459051501902504 75
UVM_INFO @ 323206719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 50964439794373267711104030829590972171334897426304473498497557315363883761730 77
UVM_INFO @ 204002369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 51050992327220894151272415393775477259285737483795079968238408864591492102554 76
UVM_INFO @ 778081561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---