Simulation Results: spi_device/1r1w

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.02 %
  • code
  • 92.75 %
  • assert
  • 94.64 %
  • func
  • 73.66 %
  • line
  • 99.03 %
  • branch
  • 98.23 %
  • cond
  • 95.73 %
  • toggle
  • 83.54 %
  • FSM
  • 87.23 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 111.760s 78465.671us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.210s 254.162us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.130s 643.357us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 15.530s 721.242us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 11.050s 1632.525us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.760s 139.148us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.130s 643.357us 1 1 100.00
spi_device_csr_aliasing 11.050s 1632.525us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.680s 12.268us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.690s 55.243us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.700s 17.486us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.860s 1.807us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.840s 3.441us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 4.510s 146.302us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 4.510s 146.302us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 1.900s 1261.675us 1 1 100.00
spi_device_tpm_sts_read 1.000s 223.039us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 1.940s 520.660us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 21.720s 9348.796us 1 1 100.00
spi_device_flash_all 39.140s 21998.937us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.720s 1280.544us 1 1 100.00
spi_device_flash_all 39.140s 21998.937us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.720s 1280.544us 1 1 100.00
spi_device_flash_all 39.140s 21998.937us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 39.140s 21998.937us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 9.470s 1068.855us 1 1 100.00
spi_device_flash_all 39.140s 21998.937us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 9.470s 1068.855us 1 1 100.00
spi_device_flash_all 39.140s 21998.937us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 9.470s 1068.855us 1 1 100.00
spi_device_flash_all 39.140s 21998.937us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 9.470s 1068.855us 1 1 100.00
spi_device_flash_all 39.140s 21998.937us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 9.470s 1068.855us 1 1 100.00
spi_device_flash_all 39.140s 21998.937us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 5.070s 5006.017us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 11.580s 2476.341us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 11.580s 2476.341us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 11.580s 2476.341us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 12.750s 4412.692us 1 1 100.00
spi_device_read_buffer_direct 4.100s 416.288us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 11.580s 2476.341us 1 1 100.00
spi_device_flash_all 39.140s 21998.937us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 39.140s 21998.937us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 39.140s 21998.937us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 1.910s 485.937us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 1.910s 485.937us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 111.760s 78465.671us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 215.840s 65235.083us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 264.420s 46389.055us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.660s 13.572us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.700s 18.277us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.480s 256.283us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.480s 256.283us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.210s 254.162us 1 1 100.00
spi_device_csr_rw 1.130s 643.357us 1 1 100.00
spi_device_csr_aliasing 11.050s 1632.525us 1 1 100.00
spi_device_same_csr_outstanding 1.440s 37.636us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.210s 254.162us 1 1 100.00
spi_device_csr_rw 1.130s 643.357us 1 1 100.00
spi_device_csr_aliasing 11.050s 1632.525us 1 1 100.00
spi_device_same_csr_outstanding 1.440s 37.636us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.010s 40.907us 1 1 100.00
spi_device_tl_intg_err 12.140s 2791.656us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 12.140s 2791.656us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 28.960s 3785.731us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
spi_device_mem_parity 12560519640262194410824620810591685081392734148224353646462799359617422934671 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1238380 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1238380 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[968])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])
spi_device_ram_cfg 98386958712270153960823619894759934996983426966650878439361780869822400994586 76
UVM_ERROR @ 789385 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe03e89 [111000000011111010001001] vs 0x0 [0])
UVM_ERROR @ 873385 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x80c418 [100000001100010000011000] vs 0x0 [0])
UVM_ERROR @ 905385 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbd0ee5 [101111010000111011100101] vs 0x0 [0])
UVM_ERROR @ 981385 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd8373b [110110000011011100111011] vs 0x0 [0])