Simulation Results: spi_device/2p

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.26 %
  • code
  • 94.07 %
  • assert
  • 94.62 %
  • func
  • 64.09 %
  • line
  • 99.07 %
  • branch
  • 98.30 %
  • cond
  • 95.90 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 47.200s 4155.067us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.050s 20.291us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.050s 106.978us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 16.790s 363.237us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 16.830s 4325.198us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.550s 118.679us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.050s 106.978us 1 1 100.00
spi_device_csr_aliasing 16.830s 4325.198us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.840s 17.087us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.350s 41.509us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.710s 20.772us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 1.380s 46.581us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.730s 42.715us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.820s 69.134us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.820s 69.134us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 19.910s 45927.018us 1 1 100.00
spi_device_tpm_sts_read 1.240s 109.465us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 18.020s 8127.565us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 3.560s 335.681us 1 1 100.00
spi_device_flash_all 62.930s 26582.761us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.980s 8229.911us 1 1 100.00
spi_device_flash_all 62.930s 26582.761us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.980s 8229.911us 1 1 100.00
spi_device_flash_all 62.930s 26582.761us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 62.930s 26582.761us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 7.860s 816.198us 1 1 100.00
spi_device_flash_all 62.930s 26582.761us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 7.860s 816.198us 1 1 100.00
spi_device_flash_all 62.930s 26582.761us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 7.860s 816.198us 1 1 100.00
spi_device_flash_all 62.930s 26582.761us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 7.860s 816.198us 1 1 100.00
spi_device_flash_all 62.930s 26582.761us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 7.860s 816.198us 1 1 100.00
spi_device_flash_all 62.930s 26582.761us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.030s 127.688us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 10.480s 16079.977us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 10.480s 16079.977us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 10.480s 16079.977us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 6.510s 7964.101us 1 1 100.00
spi_device_read_buffer_direct 8.100s 2810.899us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 10.480s 16079.977us 1 1 100.00
spi_device_flash_all 62.930s 26582.761us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 62.930s 26582.761us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 62.930s 26582.761us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.600s 1343.889us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.600s 1343.889us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 47.200s 4155.067us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 80.760s 22781.309us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 0.870s 109.221us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.730s 16.949us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.750s 50.276us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.310s 103.567us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.310s 103.567us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.050s 20.291us 1 1 100.00
spi_device_csr_rw 2.050s 106.978us 1 1 100.00
spi_device_csr_aliasing 16.830s 4325.198us 1 1 100.00
spi_device_same_csr_outstanding 3.390s 61.648us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.050s 20.291us 1 1 100.00
spi_device_csr_rw 2.050s 106.978us 1 1 100.00
spi_device_csr_aliasing 16.830s 4325.198us 1 1 100.00
spi_device_same_csr_outstanding 3.390s 61.648us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.240s 248.727us 1 1 100.00
spi_device_tl_intg_err 15.040s 4918.468us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 15.040s 4918.468us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 19.740s 4787.199us 1 1 100.00