Simulation Results: sram_ctrl/main

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.56 %
  • code
  • 96.48 %
  • assert
  • 96.19 %
  • func
  • 91.00 %
  • block
  • 95.74 %
  • line
  • 96.36 %
  • branch
  • 93.52 %
  • toggle
  • 96.04 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 6848.004us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 20.269us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 51.407us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 311.653us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 38.397us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 1043.757us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 51.407us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 38.397us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 194.000s 14429.228us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 52.000s 10013.616us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 26.000s 17433.826us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 119.000s 7204.637us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 109.000s 2970.943us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 48.000s 38685.404us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 28.000s 8733.416us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 22.000s 18767.691us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 361.338us 1 1 100.00
sram_ctrl_partial_access_b2b 200.000s 27188.277us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 703.533us 1 1 100.00
sram_ctrl_throughput_w_partial_write 7.000s 1393.924us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 1397.687us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 10.000s 3276.979us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 694.616us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 415.000s 661215.202us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 46.474us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 84.594us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 84.594us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 20.269us 1 1 100.00
sram_ctrl_csr_rw 2.000s 51.407us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 38.397us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 45.579us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 20.269us 1 1 100.00
sram_ctrl_csr_rw 2.000s 51.407us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 38.397us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 45.579us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 30.000s 24299.574us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 362.715us 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 78.476us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 362.715us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 78.476us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 3276.979us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 3276.979us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 51.407us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 22.000s 18767.691us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 22.000s 18767.691us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 22.000s 18767.691us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 28.000s 8733.416us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 712.418us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 30.000s 24299.574us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.000s 2687.958us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 6848.004us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 6848.004us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 22.000s 18767.691us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 362.715us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 28.000s 8733.416us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 362.715us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 362.715us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 6848.004us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 362.715us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 37.000s 8166.438us 1 1 100.00