Simulation Results: sram_ctrl/ret

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.21 %
  • code
  • 83.01 %
  • assert
  • 96.43 %
  • func
  • 94.20 %
  • block
  • 93.32 %
  • line
  • 94.37 %
  • branch
  • 88.73 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
87.50%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 45.383us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 50.204us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.111us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 246.016us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.067us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 35.140us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 13.111us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.067us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 7.000s 141.965us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 109.999us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 5.000s 1567.188us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 96.000s 1838.493us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 4.000s 218.589us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 12.000s 1601.131us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.000s 2544.554us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 8.000s 600.080us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.000s 25.174us 1 1 100.00
sram_ctrl_partial_access_b2b 110.000s 9802.678us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 145.875us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 187.075us 1 1 100.00
sram_ctrl_throughput_w_readback 1.000s 34.109us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 7.000s 986.586us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 30.856us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 8.000s 869.272us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 22.137us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 301.876us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 301.876us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 50.204us 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.111us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.067us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 47.466us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 50.204us 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.111us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.067us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 47.466us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 413.587us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 5.000s 1007.242us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 1993.190us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 5.000s 1007.242us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 1993.190us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 986.586us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 986.586us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.111us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 8.000s 600.080us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 8.000s 600.080us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 8.000s 600.080us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.000s 2544.554us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 131.385us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 413.587us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 125.967us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 45.383us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 45.383us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 8.000s 600.080us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 5.000s 1007.242us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.000s 2544.554us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 5.000s 1007.242us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 1007.242us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 45.383us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 1007.242us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 8.000s 622.053us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (tl_host_driver.sv:121) [driver] Check failed seq_item_port.has_do_available() == * (* [*] vs * [*])
sram_ctrl_csr_mem_rw_with_rand_reset 60992882625212863238985944109508866214386468893287363983427322259089312312546 92
UVM_INFO @ 35139916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---