Simulation Results: sysrst_ctrl

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.79 %
  • code
  • 90.42 %
  • assert
  • 87.45 %
  • func
  • 70.51 %
  • line
  • 95.85 %
  • branch
  • 96.44 %
  • cond
  • 93.16 %
  • toggle
  • 100.00 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.490s 2139.711us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 5.790s 2463.611us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 2.870s 2419.252us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.450s 2363.766us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 2.520s 4049.376us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 1.280s 2253.519us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 51.750s 31187.451us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 7.780s 2541.044us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.310s 2046.425us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 1.280s 2253.519us 1 1 100.00
sysrst_ctrl_csr_aliasing 7.780s 2541.044us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 27.360s 30063.306us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 11.380s 80547.404us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 3.610s 3050.314us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 4.860s 3167.429us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.840s 2537.616us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 4.150s 2017.057us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 2.460s 2937.591us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 5.660s 2610.901us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 3.570s 6397.660us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 33.410s 35416.688us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 9.650s 10503.315us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 2.170s 2041.810us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.640s 2012.943us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 2.840s 2033.559us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 2.840s 2033.559us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.520s 4049.376us 1 1 100.00
sysrst_ctrl_csr_rw 1.280s 2253.519us 1 1 100.00
sysrst_ctrl_csr_aliasing 7.780s 2541.044us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.310s 4415.448us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.520s 4049.376us 1 1 100.00
sysrst_ctrl_csr_rw 1.280s 2253.519us 1 1 100.00
sysrst_ctrl_csr_aliasing 7.780s 2541.044us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.310s 4415.448us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 76.740s 42010.084us 1 1 100.00
sysrst_ctrl_tl_intg_err 11.410s 43422.336us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 11.410s 43422.336us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 9.070s 16665.156us 1 1 100.00