Simulation Results: uart

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.74 %
  • code
  • 95.99 %
  • assert
  • 97.12 %
  • func
  • 52.11 %
  • line
  • 99.17 %
  • branch
  • 96.97 %
  • cond
  • 96.27 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.310s 672.221us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.570s 25.288us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.780s 29.809us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.140s 209.439us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.780s 97.669us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.840s 217.521us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.780s 29.809us 1 1 100.00
uart_csr_aliasing 0.780s 97.669us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 60.700s 218998.922us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.310s 672.221us 1 1 100.00
uart_tx_rx 60.700s 218998.922us 1 1 100.00
parity_error 2 2 100.00
uart_intr 11.440s 50644.558us 1 1 100.00
uart_rx_parity_err 56.140s 56419.077us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 60.700s 218998.922us 1 1 100.00
uart_intr 11.440s 50644.558us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 12.100s 44699.626us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 186.010s 180935.452us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 48.050s 135742.532us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 11.440s 50644.558us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 11.440s 50644.558us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 11.440s 50644.558us 1 1 100.00
perf 1 1 100.00
uart_perf 107.000s 13747.838us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.690s 7659.618us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.690s 7659.618us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 21.890s 67750.440us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.730s 1891.994us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.910s 519.918us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 9.530s 5575.592us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 117.720s 45439.800us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 24.190s 22678.041us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.550s 45.625us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.610s 47.101us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.560s 235.923us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.560s 235.923us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.570s 25.288us 1 1 100.00
uart_csr_rw 0.780s 29.809us 1 1 100.00
uart_csr_aliasing 0.780s 97.669us 1 1 100.00
uart_same_csr_outstanding 0.870s 158.231us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.570s 25.288us 1 1 100.00
uart_csr_rw 0.780s 29.809us 1 1 100.00
uart_csr_aliasing 0.780s 97.669us 1 1 100.00
uart_same_csr_outstanding 0.870s 158.231us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.140s 1077.684us 1 1 100.00
uart_tl_intg_err 1.060s 781.338us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.060s 781.338us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 30.820s 8227.075us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = *
uart_noise_filter 39896851755050944223528978018460115026966574929358455527312828033275927205772 80
UVM_ERROR @ 64477676757 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 64477676757 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 64592545633 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 64592632589 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (47 [0x2f] vs 253 [0xfd]) reg name: uart_reg_block.rdata