Simulation Results: adc_ctrl

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.44 %
  • code
  • 92.22 %
  • assert
  • 90.92 %
  • func
  • 13.19 %
  • line
  • 97.94 %
  • branch
  • 96.29 %
  • cond
  • 86.02 %
  • toggle
  • 99.76 %
  • FSM
  • 81.08 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 10.620s 5724.403us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.000s 838.279us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.460s 354.587us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 22.710s 48441.281us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.640s 720.002us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.070s 616.164us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.460s 354.587us 1 1 100.00
adc_ctrl_csr_aliasing 2.640s 720.002us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 0.900s 290.821us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 0.860s 323.481us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.800s 412.887us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 1.360s 409.122us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.990s 276.191us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.830s 285.215us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 0.840s 309.534us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 1.020s 357.236us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 7.140s 4228.811us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 20.210s 37951.424us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 76.600s 83029.782us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 1.000s 820.215us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.590s 344.752us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.270s 367.605us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.260s 584.774us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.260s 584.774us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.000s 838.279us 1 1 100.00
adc_ctrl_csr_rw 1.460s 354.587us 1 1 100.00
adc_ctrl_csr_aliasing 2.640s 720.002us 1 1 100.00
adc_ctrl_same_csr_outstanding 6.080s 2124.589us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.000s 838.279us 1 1 100.00
adc_ctrl_csr_rw 1.460s 354.587us 1 1 100.00
adc_ctrl_csr_aliasing 2.640s 720.002us 1 1 100.00
adc_ctrl_same_csr_outstanding 6.080s 2124.589us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 7.330s 4176.138us 1 1 100.00
adc_ctrl_tl_intg_err 4.020s 4456.709us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 4.020s 4456.709us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 3.340s 2022.830us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *]
adc_ctrl_filters_polled 103481853773147691638391351371719524135068405867356191404071049830733255664051 389
UVM_INFO @ 290821417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 104821014575555716526350970676864150945911501148635971832420436718636743573699 389
UVM_INFO @ 323480727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 19205242098418482618047807440277713059617159993390790965540913789658687365903 389
UVM_INFO @ 412887475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 21134075743852355786393386276330632456373333975940443260255821605742467756955 389
UVM_INFO @ 409121747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 40080384217369949593657504269719921349686973983747596803640756236947172517181 389
UVM_INFO @ 276190735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 59858624639680806353715306381699410994754933100864963245897531432460326750719 389
UVM_INFO @ 285215458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 78723575718805692546035482919163712651404821861871213980598089382534102447867 389
UVM_INFO @ 357235540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 110560713012812748655415175803614068440371907446210548674245985775019519408528 389
UVM_INFO @ 309533780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 58992703631160287085927760203703420636548655168528045501408477903317086061500 424
UVM_INFO @ 2022830191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 10845100106777881865060855201929505624865883363664573724143558158688453381518 390
UVM_INFO @ 820215378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---