Simulation Results: aes/masked

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.01 %
  • code
  • 95.68 %
  • assert
  • 98.29 %
  • func
  • 64.07 %
  • block
  • 95.93 %
  • line
  • 97.49 %
  • branch
  • 89.92 %
  • toggle
  • 97.88 %
  • FSM
  • 97.42 %
Validation stages
V1
100.00%
V2
94.74%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 59.674us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 59.194us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 66.251us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 81.270us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 625.899us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 4.000s 539.150us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 141.553us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 81.270us 1 1 100.00
aes_csr_aliasing 4.000s 539.150us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 59.194us 1 1 100.00
aes_config_error 3.000s 259.750us 1 1 100.00
aes_stress 5.000s 111.036us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 59.194us 1 1 100.00
aes_config_error 3.000s 259.750us 1 1 100.00
aes_stress 5.000s 111.036us 1 1 100.00
back2back 2 2 100.00
aes_stress 5.000s 111.036us 1 1 100.00
aes_b2b 12.000s 379.083us 1 1 100.00
backpressure 1 1 100.00
aes_stress 5.000s 111.036us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 59.194us 1 1 100.00
aes_config_error 3.000s 259.750us 1 1 100.00
aes_stress 5.000s 111.036us 1 1 100.00
aes_alert_reset 9.000s 10088.453us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 62.882us 1 1 100.00
aes_config_error 3.000s 259.750us 1 1 100.00
aes_alert_reset 9.000s 10088.453us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 276.769us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 246.235us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 12.000s 3554.005us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 9.000s 10088.453us 0 1 0.00
stress 1 1 100.00
aes_stress 5.000s 111.036us 1 1 100.00
sideload 2 2 100.00
aes_stress 5.000s 111.036us 1 1 100.00
aes_sideload 4.000s 138.824us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 196.168us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 40.000s 1581.131us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 4.000s 99.197us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 56.552us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 85.967us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 85.967us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 66.251us 1 1 100.00
aes_csr_rw 1.000s 81.270us 1 1 100.00
aes_csr_aliasing 4.000s 539.150us 1 1 100.00
aes_same_csr_outstanding 2.000s 87.413us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 66.251us 1 1 100.00
aes_csr_rw 1.000s 81.270us 1 1 100.00
aes_csr_aliasing 4.000s 539.150us 1 1 100.00
aes_same_csr_outstanding 2.000s 87.413us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 7.000s 767.893us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 32.000s 10033.059us 0 1 0.00
aes_control_fi 2.000s 60.322us 1 1 100.00
aes_cipher_fi 2.000s 74.684us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 86.388us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 86.388us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 86.388us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 86.388us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 144.360us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 1025.256us 1 1 100.00
aes_tl_intg_err 2.000s 113.264us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 113.264us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 9.000s 10088.453us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 86.388us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 86.388us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 59.194us 1 1 100.00
aes_stress 5.000s 111.036us 1 1 100.00
aes_alert_reset 9.000s 10088.453us 0 1 0.00
aes_core_fi 2.000s 66.667us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 4.000s 99.197us 1 1 100.00
aes_config_error 3.000s 259.750us 1 1 100.00
aes_stress 5.000s 111.036us 1 1 100.00
aes_core_fi 2.000s 66.667us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 86.388us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 68.279us 1 1 100.00
aes_stress 5.000s 111.036us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 5.000s 111.036us 1 1 100.00
aes_sideload 4.000s 138.824us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 68.279us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 68.279us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 68.279us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 68.279us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 68.279us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 5.000s 111.036us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 5.000s 111.036us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 32.000s 10033.059us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 32.000s 10033.059us 0 1 0.00
aes_control_fi 2.000s 60.322us 1 1 100.00
aes_cipher_fi 2.000s 74.684us 1 1 100.00
aes_ctr_fi 2.000s 90.041us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 32.000s 10033.059us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 32.000s 10033.059us 0 1 0.00
aes_control_fi 2.000s 60.322us 1 1 100.00
aes_cipher_fi 2.000s 74.684us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 74.684us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 32.000s 10033.059us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 32.000s 10033.059us 0 1 0.00
aes_control_fi 2.000s 60.322us 1 1 100.00
aes_ctr_fi 2.000s 90.041us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 32.000s 10033.059us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 32.000s 10033.059us 0 1 0.00
aes_control_fi 2.000s 60.322us 1 1 100.00
aes_cipher_fi 2.000s 74.684us 1 1 100.00
aes_ctr_fi 2.000s 90.041us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 9.000s 10088.453us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 32.000s 10033.059us 0 1 0.00
aes_control_fi 2.000s 60.322us 1 1 100.00
aes_cipher_fi 2.000s 74.684us 1 1 100.00
aes_ctr_fi 2.000s 90.041us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 32.000s 10033.059us 0 1 0.00
aes_control_fi 2.000s 60.322us 1 1 100.00
aes_cipher_fi 2.000s 74.684us 1 1 100.00
aes_ctr_fi 2.000s 90.041us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 32.000s 10033.059us 0 1 0.00
aes_control_fi 2.000s 60.322us 1 1 100.00
aes_ctr_fi 2.000s 90.041us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 32.000s 10033.059us 0 1 0.00
aes_ghash_fi 2.000s 93.163us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 32.000s 10033.059us 0 1 0.00
aes_control_fi 2.000s 60.322us 1 1 100.00
aes_cipher_fi 2.000s 74.684us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 7.000s 227.837us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 90497345695923932072639208748699657813834871316362446965003093665283237639733 3660
UVM_INFO @ 10088452976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 43572511591591894968168267317375358873871123154574959246628165716561084731171 1666
UVM_INFO @ 10033058867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
aes_stress_all_with_rand_reset 11896717705435095280965811738723288155270523742842740993198933695035709187148 110
UVM_INFO @ 227836756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---