Simulation Results: aes/unmasked

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.45 %
  • code
  • 91.48 %
  • assert
  • 97.75 %
  • func
  • 67.13 %
  • block
  • 91.08 %
  • line
  • 93.34 %
  • branch
  • 83.82 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
94.74%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 59.815us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 63.135us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 77.633us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 81.726us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 135.013us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 325.138us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 69.536us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 81.726us 1 1 100.00
aes_csr_aliasing 3.000s 325.138us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 63.135us 1 1 100.00
aes_config_error 2.000s 97.086us 1 1 100.00
aes_stress 2.000s 215.478us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 63.135us 1 1 100.00
aes_config_error 2.000s 97.086us 1 1 100.00
aes_stress 2.000s 215.478us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 215.478us 1 1 100.00
aes_b2b 4.000s 89.117us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 215.478us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 63.135us 1 1 100.00
aes_config_error 2.000s 97.086us 1 1 100.00
aes_stress 2.000s 215.478us 1 1 100.00
aes_alert_reset 32.000s 10018.278us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 69.519us 1 1 100.00
aes_config_error 2.000s 97.086us 1 1 100.00
aes_alert_reset 32.000s 10018.278us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 96.343us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 115.439us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 4.000s 105.483us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 32.000s 10018.278us 0 1 0.00
stress 1 1 100.00
aes_stress 2.000s 215.478us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 215.478us 1 1 100.00
aes_sideload 2.000s 94.257us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 202.006us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 16.000s 1318.131us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 73.369us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 62.242us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 166.760us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 166.760us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 77.633us 1 1 100.00
aes_csr_rw 2.000s 81.726us 1 1 100.00
aes_csr_aliasing 3.000s 325.138us 1 1 100.00
aes_same_csr_outstanding 1.000s 123.304us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 77.633us 1 1 100.00
aes_csr_rw 2.000s 81.726us 1 1 100.00
aes_csr_aliasing 3.000s 325.138us 1 1 100.00
aes_same_csr_outstanding 1.000s 123.304us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 244.711us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 8.000s 10031.425us 0 1 0.00
aes_control_fi 2.000s 62.812us 1 1 100.00
aes_cipher_fi 2.000s 60.136us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 73.855us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 73.855us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 73.855us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 73.855us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 611.815us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 1470.148us 1 1 100.00
aes_tl_intg_err 2.000s 204.983us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 204.983us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 32.000s 10018.278us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 73.855us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 73.855us 1 1 100.00
sec_cm_main_config_sparse 2 4 50.00
aes_smoke 2.000s 63.135us 1 1 100.00
aes_stress 2.000s 215.478us 1 1 100.00
aes_alert_reset 32.000s 10018.278us 0 1 0.00
aes_core_fi 12.000s 10022.138us 0 1 0.00
sec_cm_gcm_config_sparse 3 4 75.00
aes_gcm_save_restore 3.000s 73.369us 1 1 100.00
aes_config_error 2.000s 97.086us 1 1 100.00
aes_stress 2.000s 215.478us 1 1 100.00
aes_core_fi 12.000s 10022.138us 0 1 0.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 73.855us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 59.561us 1 1 100.00
aes_stress 2.000s 215.478us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 215.478us 1 1 100.00
aes_sideload 2.000s 94.257us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 59.561us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 59.561us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 59.561us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 59.561us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 59.561us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 215.478us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 215.478us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 8.000s 10031.425us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 8.000s 10031.425us 0 1 0.00
aes_control_fi 2.000s 62.812us 1 1 100.00
aes_cipher_fi 2.000s 60.136us 1 1 100.00
aes_ctr_fi 1.000s 60.711us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 8.000s 10031.425us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 8.000s 10031.425us 0 1 0.00
aes_control_fi 2.000s 62.812us 1 1 100.00
aes_cipher_fi 2.000s 60.136us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 60.136us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 8.000s 10031.425us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 8.000s 10031.425us 0 1 0.00
aes_control_fi 2.000s 62.812us 1 1 100.00
aes_ctr_fi 1.000s 60.711us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 8.000s 10031.425us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 8.000s 10031.425us 0 1 0.00
aes_control_fi 2.000s 62.812us 1 1 100.00
aes_cipher_fi 2.000s 60.136us 1 1 100.00
aes_ctr_fi 1.000s 60.711us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 32.000s 10018.278us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 8.000s 10031.425us 0 1 0.00
aes_control_fi 2.000s 62.812us 1 1 100.00
aes_cipher_fi 2.000s 60.136us 1 1 100.00
aes_ctr_fi 1.000s 60.711us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 8.000s 10031.425us 0 1 0.00
aes_control_fi 2.000s 62.812us 1 1 100.00
aes_cipher_fi 2.000s 60.136us 1 1 100.00
aes_ctr_fi 1.000s 60.711us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 8.000s 10031.425us 0 1 0.00
aes_control_fi 2.000s 62.812us 1 1 100.00
aes_ctr_fi 1.000s 60.711us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 8.000s 10031.425us 0 1 0.00
aes_ghash_fi 1.000s 61.551us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 8.000s 10031.425us 0 1 0.00
aes_control_fi 2.000s 62.812us 1 1 100.00
aes_cipher_fi 2.000s 60.136us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 11.000s 278.164us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 29365130923258770609620131315037172587011343991221937536127904844615156468992 1189
UVM_INFO @ 10018278366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 114187208114468455340482340303427397639797812478253826783673149447389144097733 1748
UVM_INFO @ 10031425453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred!
aes_core_fi 15094695487608129809934665267642660637097447117023287950275935146021327173816 153
UVM_INFO @ 10022137702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 80016202889141682925053012487061340241992251959786362395235465401005551618072 519
UVM_INFO @ 278164411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---