Simulation Results: chip

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.92 %
  • code
  • 85.05 %
  • assert
  • 97.25 %
  • func
  • 45.45 %
  • line
  • 94.32 %
  • branch
  • 93.54 %
  • cond
  • 88.98 %
  • toggle
  • 91.27 %
  • FSM
  • 57.14 %
Validation stages
V1
100.00%
V2
78.06%
V2S
100.00%
V3
69.23%
unmapped
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 157.350s 2810.349us 1 1 100.00
chip_sw_example_rom 87.800s 2852.920us 1 1 100.00
chip_sw_example_manufacturer 145.590s 2768.074us 1 1 100.00
chip_sw_example_concurrency 129.380s 2818.347us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 148.870s 4530.575us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 318.190s 4385.466us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 611.000s 11177.676us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 4313.400s 35584.565us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
chip_csr_mem_rw_with_rand_reset 724.830s 10755.706us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 4313.400s 35584.565us 1 1 100.00
chip_csr_rw 318.190s 4385.466us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 7.500s 204.542us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 309.190s 4576.680us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 309.190s 4576.680us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 309.190s 4576.680us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 341.180s 4201.839us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 341.180s 4201.839us 1 1 100.00
chip_sw_uart_tx_rx_idx1 410.700s 4839.197us 1 1 100.00
chip_sw_uart_tx_rx_idx2 328.600s 3694.454us 1 1 100.00
chip_sw_uart_tx_rx_idx3 351.140s 3927.141us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 887.780s 7506.211us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1117.450s 8848.791us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 286.730s 4761.212us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 171.250s 4152.281us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 171.250s 4152.281us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 188.650s 3873.875us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 359.370s 5983.970us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 190.390s 4525.789us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 104.960s 2698.260us 1 1 100.00
chip_tap_straps_testunlock0 341.390s 6400.845us 1 1 100.00
chip_tap_straps_rma 152.430s 2928.561us 1 1 100.00
chip_tap_straps_prod 1013.630s 16681.455us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 202.010s 3393.802us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 759.890s 9378.825us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 439.500s 6379.705us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 439.500s 6379.705us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 638.030s 8083.259us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 735.460s 9539.578us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 371.920s 4192.792us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 626.410s 5787.218us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3830.440s 19174.346us 1 1 100.00
chip_sw_aes_enc_jitter_en 154.790s 3095.528us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 562.300s 6130.881us 1 1 100.00
chip_sw_hmac_enc_jitter_en 140.680s 2807.480us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 817.680s 7205.692us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 201.900s 3519.769us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 338.500s 4360.757us 1 1 100.00
chip_sw_clkmgr_jitter 162.020s 3480.364us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 203.570s 3365.845us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 480.800s 7385.634us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 256.800s 5142.995us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 118.560s 2511.202us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 256.800s 5142.995us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 175.890s 3148.376us 1 1 100.00
chip_sw_aes_smoketest 204.660s 2760.819us 1 1 100.00
chip_sw_aon_timer_smoketest 192.850s 2727.235us 1 1 100.00
chip_sw_clkmgr_smoketest 121.100s 3115.337us 1 1 100.00
chip_sw_csrng_smoketest 138.480s 3170.491us 1 1 100.00
chip_sw_entropy_src_smoketest 1046.190s 7726.395us 1 1 100.00
chip_sw_gpio_smoketest 162.780s 2909.686us 1 1 100.00
chip_sw_hmac_smoketest 174.030s 2854.838us 1 1 100.00
chip_sw_kmac_smoketest 187.300s 3044.380us 1 1 100.00
chip_sw_otbn_smoketest 1126.670s 9374.490us 1 1 100.00
chip_sw_pwrmgr_smoketest 338.680s 6627.897us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 284.820s 5717.570us 1 1 100.00
chip_sw_rv_plic_smoketest 170.490s 3175.488us 1 1 100.00
chip_sw_rv_timer_smoketest 133.240s 3086.741us 1 1 100.00
chip_sw_rstmgr_smoketest 126.950s 2572.881us 1 1 100.00
chip_sw_sram_ctrl_smoketest 165.690s 2801.161us 1 1 100.00
chip_sw_uart_smoketest 174.770s 2881.232us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 196.980s 3245.830us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 327.940s 5241.286us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 8161.160s 63090.491us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3053.890s 16111.792us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 30.891s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 208.010s 3753.073us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 208.410s 3335.484us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7272.150s 55882.701us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7873.250s 58227.267us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 42.550s 2174.614us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 42.550s 2174.614us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 4313.400s 35584.565us 1 1 100.00
chip_same_csr_outstanding 1146.030s 15943.885us 1 1 100.00
chip_csr_hw_reset 148.870s 4530.575us 1 1 100.00
chip_csr_rw 318.190s 4385.466us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 4313.400s 35584.565us 1 1 100.00
chip_same_csr_outstanding 1146.030s 15943.885us 1 1 100.00
chip_csr_hw_reset 148.870s 4530.575us 1 1 100.00
chip_csr_rw 318.190s 4385.466us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 31.800s 321.807us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 5.460s 51.394us 1 1 100.00
xbar_smoke_large_delays 43.800s 7223.530us 1 1 100.00
xbar_smoke_slow_rsp 43.950s 4837.145us 1 1 100.00
xbar_random_zero_delays 9.380s 108.169us 1 1 100.00
xbar_random_large_delays 29.340s 4578.045us 1 1 100.00
xbar_random_slow_rsp 144.110s 14742.820us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 22.960s 807.914us 1 1 100.00
xbar_error_and_unmapped_addr 17.560s 653.216us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 20.390s 919.598us 1 1 100.00
xbar_error_and_unmapped_addr 17.560s 653.216us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 88.490s 3482.019us 1 1 100.00
xbar_access_same_device_slow_rsp 627.440s 69647.616us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 39.430s 1677.085us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 178.510s 3188.095us 1 1 100.00
xbar_stress_all_with_error 127.010s 4845.942us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 42.040s 74.252us 1 1 100.00
xbar_stress_all_with_reset_error 97.680s 424.456us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3053.890s 16111.792us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2751.490s 30340.451us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2831.220s 15254.564us 1 1 100.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 51.060s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 9.393s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 10.008s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 9.981s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 22.125s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 133.797s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 52.084s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 26.701s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 24.424s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 35.969s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 200.504s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 85.646s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 57.519s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 53.165s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 123.886s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 25.320s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 19.310s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 16.690s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 21.290s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 18.420s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 15.920s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 16.470s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 16.910s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 17.880s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 18.100s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 22.370s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 16.710s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 16.830s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 22.430s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 18.950s 10.260us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 66.479s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 88.925s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 80.868s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 77.899s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 79.462s 0.000us 0 1 0.00
rom_e2e_keymgr_init 2 3 66.67
rom_e2e_keymgr_init_rom_ext_meas 5977.810s 28850.755us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 5808.210s 28461.906us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 3151.490s 16675.783us 0 1 0.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3207.610s 15706.694us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3134.160s 34099.406us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3134.160s 34099.406us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 171.180s 3007.973us 1 1 100.00
chip_sw_aes_enc_jitter_en 154.790s 3095.528us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 136.020s 3524.081us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 129.420s 2474.827us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1759.180s 12804.805us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 174.980s 3111.755us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 287.880s 5421.637us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 414.510s 5636.452us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 587.410s 5774.335us 1 1 100.00
chip_plic_all_irqs_10 286.470s 3384.223us 1 1 100.00
chip_plic_all_irqs_20 422.700s 5043.951us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 210.850s 3725.691us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1288.840s 16385.679us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 231.020s 4508.581us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 117.730s 2840.645us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 986.060s 8116.279us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 959.270s 6907.956us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 880.500s 8706.896us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 9006.230s 255579.288us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 284.490s 4302.791us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 338.680s 6627.897us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 284.490s 4302.791us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 519.790s 8423.072us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 519.790s 8423.072us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 374.830s 8141.156us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 358.960s 5760.584us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 605.330s 5965.961us 1 1 100.00
chip_sw_aes_idle 129.420s 2474.827us 1 1 100.00
chip_sw_hmac_enc_idle 196.620s 3086.862us 1 1 100.00
chip_sw_kmac_idle 175.780s 2844.940us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 219.500s 3538.513us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 257.100s 4163.753us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 313.090s 5522.946us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 237.850s 4534.160us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 750.300s 10198.233us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 386.700s 4620.654us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 404.230s 5275.180us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 439.950s 4347.578us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 378.740s 4549.701us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 482.720s 4809.462us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 373.650s 4589.883us 1 1 100.00
chip_sw_ast_clk_outputs 638.030s 8083.259us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 587.280s 13180.383us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 439.950s 4347.578us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 378.740s 4549.701us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 371.920s 4192.792us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 626.410s 5787.218us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3830.440s 19174.346us 1 1 100.00
chip_sw_aes_enc_jitter_en 154.790s 3095.528us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 562.300s 6130.881us 1 1 100.00
chip_sw_hmac_enc_jitter_en 140.680s 2807.480us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 817.680s 7205.692us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 201.900s 3519.769us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 338.500s 4360.757us 1 1 100.00
chip_sw_clkmgr_jitter 162.020s 3480.364us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 124.750s 2384.054us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 376.180s 4564.173us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 642.470s 6749.610us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4050.530s 25586.886us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 184.650s 3294.427us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 152.920s 3120.784us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1032.020s 10447.847us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 191.450s 3501.728us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 430.120s 5794.419us 1 1 100.00
chip_sw_flash_init_reduced_freq 1152.000s 24962.155us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 4617.260s 34896.407us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 638.030s 8083.259us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 373.170s 4933.201us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 291.900s 4368.389us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 414.510s 5636.452us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 986.060s 8116.279us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2157.090s 23994.894us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 164.470s 3345.954us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 440.810s 6965.109us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 158.560s 2862.731us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 1996.770s 12562.297us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 138.530s 3338.523us 1 1 100.00
chip_sw_edn_entropy_reqs 703.960s 6104.951us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 138.530s 3338.523us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2157.090s 23994.894us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 141.390s 2628.380us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1074.330s 17147.494us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 593.280s 5889.682us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 626.410s 5787.218us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 338.100s 4167.374us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 371.920s 4192.792us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3467.290s 44253.863us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1074.330s 17147.494us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 258.960s 3515.569us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1645.130s 12926.648us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 204.760s 3514.098us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3467.290s 44253.863us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 204.760s 3514.098us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 204.760s 3514.098us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 204.760s 3514.098us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 204.760s 3514.098us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 414.510s 5636.452us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 448.400s 13415.040us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 582.070s 5363.941us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 423.130s 6194.651us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 423.130s 6194.651us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 151.500s 3176.575us 1 1 100.00
chip_sw_hmac_enc_jitter_en 140.680s 2807.480us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 196.620s 3086.862us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1679.130s 11447.724us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 662.570s 6181.720us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 483.650s 5220.371us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 487.780s 6027.931us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 418.850s 4916.565us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 320.760s 3778.324us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1645.130s 12926.648us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 817.680s 7205.692us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1776.490s 12241.465us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1759.180s 12804.805us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 3075.890s 16080.788us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 150.490s 2643.805us 1 1 100.00
chip_sw_kmac_mode_kmac 188.340s 3362.754us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 201.900s 3519.769us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1645.130s 12926.648us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 691.670s 12520.092us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 115.780s 3025.791us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1000.680s 8050.898us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 175.780s 2844.940us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 287.880s 5421.637us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 104.960s 2698.260us 1 1 100.00
chip_tap_straps_rma 152.430s 2928.561us 1 1 100.00
chip_tap_straps_prod 1013.630s 16681.455us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 167.120s 3039.966us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 691.670s 12520.092us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 691.670s 12520.092us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 691.670s 12520.092us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 748.850s 7481.867us 1 1 100.00
chip_sw_lc_ctrl_broadcast 20 22 90.91
chip_sw_flash_ctrl_lc_rw_en 204.760s 3514.098us 0 1 0.00
chip_sw_flash_rma_unlocked 3467.290s 44253.863us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 203.930s 3273.190us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 648.230s 7634.885us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 474.380s 6990.061us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 471.360s 6689.750us 0 1 0.00
chip_sw_lc_ctrl_transition 691.670s 12520.092us 1 1 100.00
chip_sw_keymgr_key_derivation 1645.130s 12926.648us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 297.020s 9178.579us 1 1 100.00
chip_sw_sram_ctrl_execution_main 468.000s 8737.469us 1 1 100.00
chip_prim_tl_access 448.400s 13415.040us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 587.280s 13180.383us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 386.700s 4620.654us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 404.230s 5275.180us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 439.950s 4347.578us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 378.740s 4549.701us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 482.720s 4809.462us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 373.650s 4589.883us 1 1 100.00
chip_tap_straps_dev 104.960s 2698.260us 1 1 100.00
chip_tap_straps_rma 152.430s 2928.561us 1 1 100.00
chip_tap_straps_prod 1013.630s 16681.455us 1 1 100.00
chip_rv_dm_lc_disabled 299.620s 11575.404us 1 1 100.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 187.880s 3258.704us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 73.830s 2812.352us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 90.070s 3029.201us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 145.650s 3145.725us 1 1 100.00
chip_lc_test_locked 2 2 100.00
chip_sw_lc_walkthrough_testunlocks 1709.470s 34532.791us 1 1 100.00
chip_rv_dm_lc_disabled 299.620s 11575.404us 1 1 100.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 655.630s 12779.842us 0 1 0.00
chip_sw_lc_walkthrough_prod 558.020s 9633.520us 0 1 0.00
chip_sw_lc_walkthrough_prodend 717.020s 10840.296us 1 1 100.00
chip_sw_lc_walkthrough_rma 352.530s 6113.418us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1709.470s 34532.791us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 73.080s 2889.888us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 55.430s 2015.391us 1 1 100.00
rom_volatile_raw_unlock 127.848s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3647.130s 17248.457us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3830.440s 19174.346us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 605.330s 5965.961us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 605.330s 5965.961us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 605.330s 5965.961us 1 1 100.00
chip_sw_otbn_mem_scramble 0 1 0.00
chip_sw_otbn_mem_scramble 255.810s 3715.874us 0 1 0.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 691.670s 12520.092us 1 1 100.00
chip_sw_otp_ctrl_keys 4 5 80.00
chip_sw_flash_init 1074.330s 17147.494us 1 1 100.00
chip_sw_otbn_mem_scramble 255.810s 3715.874us 0 1 0.00
chip_sw_keymgr_key_derivation 1645.130s 12926.648us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 439.050s 5369.858us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 174.380s 3317.395us 1 1 100.00
chip_sw_otp_ctrl_entropy 4 5 80.00
chip_sw_flash_init 1074.330s 17147.494us 1 1 100.00
chip_sw_otbn_mem_scramble 255.810s 3715.874us 0 1 0.00
chip_sw_keymgr_key_derivation 1645.130s 12926.648us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 439.050s 5369.858us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 174.380s 3317.395us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 691.670s 12520.092us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 366.910s 5112.196us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 167.120s 3039.966us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 203.930s 3273.190us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 648.230s 7634.885us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 474.380s 6990.061us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 471.360s 6689.750us 0 1 0.00
chip_sw_lc_ctrl_transition 691.670s 12520.092us 1 1 100.00
chip_prim_tl_access 448.400s 13415.040us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 448.400s 13415.040us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 858.850s 7204.356us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 171.910s 4912.958us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1142.760s 25481.684us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 287.940s 7598.629us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 400.730s 7819.298us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 487.590s 6148.145us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 997.480s 25364.781us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1 2 50.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 376.480s 9548.519us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 519.790s 8423.072us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 976.100s 14436.743us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 300.040s 4291.452us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 171.910s 4912.958us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 287.490s 4594.562us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 993.030s 19411.856us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 373.090s 7212.088us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 148.880s 3536.285us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1607.520s 23591.336us 1 1 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 756.080s 9541.884us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1011.710s 11384.258us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1708.060s 26677.055us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 173.350s 2997.581us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 414.510s 5636.452us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 297.020s 9178.579us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 297.020s 9178.579us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 4 4 100.00
chip_sw_pwrmgr_all_reset_reqs 1011.710s 11384.258us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1607.520s 23591.336us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 300.040s 4291.452us 1 1 100.00
chip_sw_pwrmgr_smoketest 338.680s 6627.897us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 216.780s 3394.358us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 350.360s 6422.206us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 236.030s 4847.788us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1288.840s 16385.679us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 124.620s 2695.544us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 414.510s 5636.452us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 959.270s 6907.956us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 473.950s 4434.538us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 464.480s 4731.367us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 147.890s 3362.942us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 174.380s 3317.395us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 350.360s 6422.206us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 350.360s 6422.206us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 1097.540s 16426.106us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 832.410s 13803.435us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 216.780s 3394.358us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 203.840s 3248.247us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 331.110s 6703.338us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 152.430s 2928.561us 1 1 100.00
chip_rv_dm_lc_disabled 1 1 100.00
chip_rv_dm_lc_disabled 299.620s 11575.404us 1 1 100.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 587.410s 5774.335us 1 1 100.00
chip_plic_all_irqs_10 286.470s 3384.223us 1 1 100.00
chip_plic_all_irqs_20 422.700s 5043.951us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 182.390s 3141.501us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 146.530s 3169.320us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3053.890s 16111.792us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 492.680s 7765.922us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 218.160s 3680.571us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 180.740s 3664.588us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 148.790s 2943.567us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 439.050s 5369.858us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 338.500s 4360.757us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 441.610s 8347.885us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 547.150s 9444.929us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 468.000s 8737.469us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 414.510s 5636.452us 1 1 100.00
chip_sw_data_integrity_escalation 439.500s 6379.705us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 756.080s 9541.884us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1229.510s 23510.405us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 193.840s 2866.523us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 229.130s 3994.748us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 317.350s 4695.625us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1229.510s 23510.405us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1229.510s 23510.405us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2322.410s 20284.803us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2322.410s 20284.803us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 323.870s 6065.791us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3134.160s 34099.406us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 136.480s 2761.957us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 128.910s 2698.211us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 263.950s 3644.147us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 331.810s 3560.042us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 971.110s 8285.163us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5113.870s 31779.640us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1940.900s 12227.258us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 144.490s 2396.740us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 200.790s 3664.213us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 118.020s 2767.413us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 10221.720s 71733.202us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1109.270s 6966.511us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 159.670s 3526.860us 0 1 0.00
rom_e2e_jtag_debug_dev 131.850s 2902.411us 0 1 0.00
rom_e2e_jtag_debug_rma 190.380s 3728.537us 0 1 0.00
rom_e2e_jtag_inject 1 3 33.33
rom_e2e_jtag_inject_test_unlocked0 65.460s 2026.676us 0 1 0.00
rom_e2e_jtag_inject_dev 53.440s 1996.825us 0 1 0.00
rom_e2e_jtag_inject_rma 186.230s 4506.122us 1 1 100.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 131.021s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 262.600s 3566.364us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 316.250s 3215.675us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 846.970s 5793.481us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1142.210s 8798.781us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 222.600s 2266.462us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 606.040s 5132.665us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 73.290s 2390.135us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 153.650s 3392.128us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 342.480s 6946.857us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 340.050s 5018.235us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1011.710s 11384.258us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 159.670s 3526.860us 0 1 0.00
rom_e2e_jtag_debug_dev 131.850s 2902.411us 0 1 0.00
rom_e2e_jtag_debug_rma 190.380s 3728.537us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 281.050s 5667.654us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 414.510s 5636.452us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5790.020s 38776.392us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5790.020s 38776.392us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 140.310s 3123.102us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 341.180s 4201.839us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3064.560s 19039.720us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 8 10 80.00
chip_sival_flash_info_access 173.410s 2788.318us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 429.360s 5441.303us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 4.720s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 152.580s 2523.604us 1 1 100.00
chip_sw_otp_ctrl_descrambling 175.450s 3517.010us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 256.800s 3759.574us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 7.819s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 205.700s 3712.589us 1 1 100.00
ate_bootstrap_flash_erase 6766.120s 45355.488us 1 1 100.00
ate_bootstrap_disjoint 9464.060s 83994.723us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 35956005958685390101429992056887180361229680404225424781839778839531867776762 320
UVM_INFO @ 3680.570504 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_flash_ctrl_lc_rw_en 97242498718958094964661119586688726345254324220410047214051409638167024973157 309
UVM_INFO @ 3514.098405 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 68060107695919169815731379942579553176585611789435564721097769547221024320463 342
UVM_INFO @ 6689.750197 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 76170465302073825125870486313686798628283810720046350623835787242690209602245 316
UVM_ERROR @ 3392.127760 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3392.127760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 19999215292614092337804149649111534142542747352410811917281888671552188358239 312
UVM_ERROR @ 3345.954316 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3345.954316 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
chip_sw_otp_ctrl_rot_auth_config 100526073434690571461554900163715970102470217780127568479033660114335878299642 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_lc_walkthrough_dev 74085259754240815074065834142097886070043372143354971661601892216484332146005 369
UVM_INFO @ 12779.841736 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 14475803324998532958349568183786750232388788392539811212398295717277020947449 369
UVM_INFO @ 9633.519890 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 11563613366545375966697249246403227154840317560445056023692781497563047038218 341
UVM_INFO @ 6113.417755 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'
chip_sw_pwrmgr_full_aon_reset 63070555589092602749760565463663983276713992755633805276802583565855898107607 318
UVM_ERROR @ 4912.958077 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 4912.958077 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 68020197486327331569266091415108974263412678712983197095444167999557239690230 327
UVM_ERROR @ 9548.519000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9548.519000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 43231632350704476996960822259537586408174689062852680162268993313368062381506 325
UVM_ERROR @ 7819.298000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7819.298000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'
chip_sw_pwrmgr_sleep_power_glitch_reset 93363234287066283499833004275561853342596897892642025765452050321040242108287 313
UVM_ERROR @ 3536.285476 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3536.285476 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 103240157399736402736654849869984556878655604635997806640565673491188738617770 395
UVM_ERROR @ 19411.855974 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 19411.855974 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 80331691832030153235435549832508037261351600030933945849020100964161847500356 332
UVM_INFO @ 34099.406284 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otbn_mem_scramble_test_sim_dv(sw/device/tests/otbn_mem_scramble_test.c:260)] CHECK-fail: Expecting at least * DMEM integrity errors, got *
chip_sw_otbn_mem_scramble 14261103816484050745959615375953350148294557291319502077215481997244510423102 310
UVM_INFO @ 3715.873596 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:382)] CHECK-fail: Expect alert *!
chip_sw_alert_test 24014447242390935252511050542111279876770174994556948990329079733182015316806 307
UVM_INFO @ 3111.754691 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 15806361768441571441071883986058140879324957390090889510036949043803693082971 308
UVM_INFO @ 2840.644675 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed!
chip_sw_alert_handler_lpg_sleep_mode_pings 8706612446599835557996887296578932082011711176200254112147824312543894904774 None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).
chip_tl_errors 100191804536616264183546920035756677793155169958512436525056939211954384361114 217
TL item was: req: (cip_tl_seq_item@34497) { a_addr: 'h10744 a_data: 'h9b59143b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1c a_opcode: 'h4 a_user: 'h1bd8d d_param: 'h0 d_source: 'h1c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2174.614466 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_clkmgr_jitter_frequency 107688871157545958545849892170567782201479199957959465634514148396179046493814 343
UVM_INFO @ 3566.364016 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']
chip_sw_pwrmgr_sleep_wake_5_bug 44083963277277421345353252594158897062808334281774910585144189954735869577332 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 47967673912339931195087274902514160007004264981301856981141027841905575353090 None
Another command (pid=419997) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=418376) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=435177) is running. Waiting for it to complete on the server (server_pid=253193)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 56209469208933862902111573344029696671849676520348037070274585955877815328016 None
Another command (pid=520592) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=524963) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=454779) is running. Waiting for it to complete on the server (server_pid=253193)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 67492944098376332747033560391462421263113569469958310791347377784230383691976 None
Another command (pid=546006) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=557776) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=367580) is running. Waiting for it to complete on the server (server_pid=253193)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 11169496547359661370184495482520519688373054292164709799298375722000818238001 None
Another command (pid=566561) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=555543) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=563781) is running. Waiting for it to complete on the server (server_pid=253193)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 112337460184893179658034963383349360389153642607695611570170983878866479985567 None
Another command (pid=593316) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=572334) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=360427) is running. Waiting for it to complete on the server (server_pid=253193)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 2253758059552529068702664413258458738747118344285573456162105372820197336102 None
Another command (pid=486676) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=537300) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=438228) is running. Waiting for it to complete on the server (server_pid=253193)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 8730050295356644757799099893688927096333554094894366501864212074858307054657 None
Another command (pid=546006) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=557776) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=367580) is running. Waiting for it to complete on the server (server_pid=253193)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 91407458126844909420249703474375550673868543055985391067404790850265501705325 None
Another command (pid=438228) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=393049) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=438587) is running. Waiting for it to complete on the server (server_pid=253193)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 47481544882003391133772899829924616265844192013220759955551461462701784562966 None
Another command (pid=561190) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=367580) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=564253) is running. Waiting for it to complete on the server (server_pid=253193)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 8764213023097376924979802381960772517438812312447303882748822868833854453497 None
Another command (pid=568715) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=574298) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=575206) is running. Waiting for it to complete on the server (server_pid=253193)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 83379453067340621381556181589393289067077313120160510736651111947675710050285 None
Another command (pid=673516) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=669690) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=668019) is running. Waiting for it to complete on the server (server_pid=253193)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 9984664018019582686062021747275886893474474812904793704436959513091582634998 None
Another command (pid=551189) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=534915) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=566561) is running. Waiting for it to complete on the server (server_pid=253193)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 114337114067446467634806155053146502422592188546348685174073380641342256404651 None
---- STDERR ----
Another command (pid=486676) is running. Waiting for it to complete on the server (server_pid=253193)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 112096087883182868595061371524446007123452681280932018122208003682583400778839 None
Another command (pid=438228) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=393049) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=438587) is running. Waiting for it to complete on the server (server_pid=253193)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 97794983545551524170485835097585802519730823275725774830698919990758108051071 None
Another command (pid=700902) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=711833) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=582235) is running. Waiting for it to complete on the server (server_pid=253193)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 11910297404038941218005677131441216904964187941036181269875324326300072027695 None
Another command (pid=360354) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=419997) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=414389) is running. Waiting for it to complete on the server (server_pid=253193)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 98516937086578786534136553470353186881525164575640832060250775461609324979804 None
Another command (pid=556694) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=557308) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=546006) is running. Waiting for it to complete on the server (server_pid=253193)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 48230003250430078436344066597646167269389196462911973999114986897576883657039 None
Another command (pid=524963) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=454779) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=436257) is running. Waiting for it to complete on the server (server_pid=253193)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 66340193450843812495249776120074608848709952563726473820961460224111925716619 None
Another command (pid=371886) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=393049) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=438587) is running. Waiting for it to complete on the server (server_pid=253193)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 3641130349885137563415187685261687152701055979528133125273368581046456637823 None
Another command (pid=438587) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=524963) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=454779) is running. Waiting for it to complete on the server (server_pid=253193)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 91989544281972781210584007156078706731226519266000048549269789644258202972315 None
Another command (pid=360427) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=592347) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=360357) is running. Waiting for it to complete on the server (server_pid=253193)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 104502462932413466557122907651093706592597272210008777147619294467821802744579 None
Another command (pid=360354) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=419997) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=418376) is running. Waiting for it to complete on the server (server_pid=253193)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 8997780392485667609781620664674742782250920222472294363330010123700417782052 None
Another command (pid=551189) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=534915) is running. Waiting for it to complete on the server (server_pid=253193)...
Another command (pid=566561) is running. Waiting for it to complete on the server (server_pid=253193)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 26617654569953952312406402669738844412017619469558905905220795124197368402969 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 103657870054841289909159178460301621024764434263361083963199762962586757420815 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 107241964860350984478533569580508288602151600812319991978580476356157950191746 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 114019963757589457223284238292114001258812956423467019136164874855875609162043 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 100373801865859210698359815900363806171008854672528155465997431867272001470274 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 112910744947633167967299390012168342806237830991997289951479301490518045935385 312
UVM_INFO @ 3753.072500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 46610168740371908366275351180370599915463838373011105494622098884554132895188 318
UVM_INFO @ 3335.484000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
chip_sw_ast_clk_rst_inputs 111423636049779266894819498148893685673258840535055894992060600649158092122577 327
UVM_INFO @ 9539.577714 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 33782196438439471015587071828314626851387174483935119503697061503319399561684 366
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 77090128497757046514577819119324445155047231686493121957022107832636905083760 325
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 36026628519851630123002458747579480098306701413129193417271425769194103615676 366
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 25295401634229198255929943523914896796223735835150227214514343772118084360517 326
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_prod 84121619503438456898707431899485206826076119244032859333008873496289919029089 368
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 24490119108016642225771676370342424182849531016610547052057436361816155136108 364
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 58338820255719392330819386975271821147192998698727615696559846250305994619498 367
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 99215732524537929043405595189521670855509001044049578468420031861069557116565 326
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 56551525439084978990032034047416821825362909611822105288535186299664092243448 328
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 2488648550745361433003616774786075303817879875056605874745637664458259599013 328
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 83293612608417539986800630808529781774288945401207508434886044009610430650378 326
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 52521960401238022707962185087887113846761275137563229816122013584787185555895 328
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 113903803241579031786476514612342743048374550426804247493879867784480449052546 326
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 82515145496633772955867578093288638738571937713774395655905069659061669023239 325
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 59898088278782719313192766464626521713610855417892765259694352590933663188351 326
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds
rom_e2e_jtag_debug_rma 112427146866341156005316025987746115773354615427893211506235024764433689020231 318
UVM_INFO @ 3728.537157 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_invalid_meas 83289014539763935413576367122944429772768760762419342060624304192958497446839 319
UVM_INFO @ 16675.782704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
rom_keymgr_functest 11165789660939870794487018570790309183034239808063117139842400240006851955772 327
UVM_ERROR @ 5241.286478 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5241.286478 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---