Simulation Results: clkmgr

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.16 %
  • code
  • 98.23 %
  • assert
  • 95.48 %
  • func
  • 85.76 %
  • line
  • 98.97 %
  • branch
  • 98.57 %
  • cond
  • 94.44 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.810s 20.850us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.740s 17.481us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.820s 22.094us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 5.480s 1024.978us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.320s 116.978us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.110s 73.905us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.820s 22.094us 1 1 100.00
clkmgr_csr_aliasing 1.320s 116.978us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.740s 41.213us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.900s 51.654us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.800s 18.813us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.710s 38.770us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.810s 20.850us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 10.740s 2355.095us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 5.910s 1222.673us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 10.740s 2355.095us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 4.560s 1551.796us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.930s 42.269us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.860s 200.136us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.860s 200.136us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.740s 17.481us 1 1 100.00
clkmgr_csr_rw 0.820s 22.094us 1 1 100.00
clkmgr_csr_aliasing 1.320s 116.978us 1 1 100.00
clkmgr_same_csr_outstanding 0.970s 65.241us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.740s 17.481us 1 1 100.00
clkmgr_csr_rw 0.820s 22.094us 1 1 100.00
clkmgr_csr_aliasing 1.320s 116.978us 1 1 100.00
clkmgr_same_csr_outstanding 0.970s 65.241us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.710s 6.047us 0 1 0.00
clkmgr_tl_intg_err 2.200s 555.191us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.850s 258.480us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.850s 258.480us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.850s 258.480us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.850s 258.480us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 1.840s 169.709us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.200s 555.191us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 10.740s 2355.095us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 5.910s 1222.673us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.850s 258.480us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.870s 31.008us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 1.100s 72.280us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.850s 43.520us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.920s 23.982us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.890s 56.785us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.820s 22.094us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.710s 6.047us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.820s 22.094us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.820s 22.094us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.710s 6.047us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.450s 780.716us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 56.320s 14736.593us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 61759946864867418308424521573752118879735989885613013469847317305136180044804 81
UVM_INFO @ 6047189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---