Simulation Results: csrng

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.50 %
  • code
  • 94.74 %
  • assert
  • 93.23 %
  • func
  • 80.54 %
  • block
  • 97.05 %
  • line
  • 97.76 %
  • branch
  • 92.59 %
  • toggle
  • 93.37 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 24.285us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 17.603us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 38.591us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 10.000s 460.380us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 72.498us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 1.000s 44.189us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 38.591us 1 1 100.00
csrng_csr_aliasing 3.000s 72.498us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 116.478us 1 1 100.00
alerts 1 1 100.00
csrng_alert 21.000s 1729.127us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 69.276us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 6.000s 321.355us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 6.000s 321.355us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 382.000s 16728.782us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 27.215us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 36.556us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 4.000s 159.087us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 4.000s 159.087us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 17.603us 1 1 100.00
csrng_csr_rw 2.000s 38.591us 1 1 100.00
csrng_csr_aliasing 3.000s 72.498us 1 1 100.00
csrng_same_csr_outstanding 2.000s 43.533us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 17.603us 1 1 100.00
csrng_csr_rw 2.000s 38.591us 1 1 100.00
csrng_csr_aliasing 3.000s 72.498us 1 1 100.00
csrng_same_csr_outstanding 2.000s 43.533us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 11.000s 390.635us 1 1 100.00
csrng_tl_intg_err 5.000s 349.965us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 13.866us 1 1 100.00
csrng_csr_rw 2.000s 38.591us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 21.000s 1729.127us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 382.000s 16728.782us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 116.478us 1 1 100.00
csrng_err 2.000s 69.276us 1 1 100.00
csrng_sec_cm 11.000s 390.635us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 4.000s 116.478us 1 1 100.00
csrng_err 2.000s 69.276us 1 1 100.00
csrng_sec_cm 11.000s 390.635us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 4.000s 116.478us 1 1 100.00
csrng_err 2.000s 69.276us 1 1 100.00
csrng_sec_cm 11.000s 390.635us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 4.000s 116.478us 1 1 100.00
csrng_err 2.000s 69.276us 1 1 100.00
csrng_sec_cm 11.000s 390.635us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 116.478us 1 1 100.00
csrng_err 2.000s 69.276us 1 1 100.00
csrng_sec_cm 11.000s 390.635us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 21.000s 1729.127us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 116.478us 1 1 100.00
csrng_err 2.000s 69.276us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 382.000s 16728.782us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 21.000s 1729.127us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 5.000s 349.965us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 116.478us 1 1 100.00
csrng_err 2.000s 69.276us 1 1 100.00
csrng_sec_cm 11.000s 390.635us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 116.478us 1 1 100.00
csrng_err 2.000s 69.276us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 116.478us 1 1 100.00
csrng_err 2.000s 69.276us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 116.478us 1 1 100.00
csrng_err 2.000s 69.276us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 116.478us 1 1 100.00
csrng_err 2.000s 69.276us 1 1 100.00
csrng_sec_cm 11.000s 390.635us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 116.478us 1 1 100.00
csrng_err 2.000s 69.276us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job killed!
csrng_stress_all_with_rand_reset 24209298679385347209733638345313243086629139988381140107565697235695795254933 None