Simulation Results: edn/edn0

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.66 %
  • code
  • 83.10 %
  • assert
  • 96.31 %
  • func
  • 80.56 %
  • line
  • 97.66 %
  • branch
  • 92.61 %
  • cond
  • 86.48 %
  • toggle
  • 87.16 %
  • FSM
  • 51.61 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.840s 47.718us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.810s 50.295us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.900s 15.178us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.890s 363.134us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.930s 52.770us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.890s 33.952us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.900s 15.178us 1 1 100.00
edn_csr_aliasing 0.930s 52.770us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.040s 32.988us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.040s 32.988us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.040s 32.988us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.840s 31.967us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.160s 305.815us 1 1 100.00
errs 1 1 100.00
edn_err 1.010s 69.198us 1 1 100.00
disable 2 2 100.00
edn_disable 0.790s 13.210us 1 1 100.00
edn_disable_auto_req_mode 0.960s 89.460us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 4.270s 334.117us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.840s 22.589us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.820s 69.065us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.060s 80.202us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.060s 80.202us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.810s 50.295us 1 1 100.00
edn_csr_rw 0.900s 15.178us 1 1 100.00
edn_csr_aliasing 0.930s 52.770us 1 1 100.00
edn_same_csr_outstanding 1.270s 47.831us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.810s 50.295us 1 1 100.00
edn_csr_rw 0.900s 15.178us 1 1 100.00
edn_csr_aliasing 0.930s 52.770us 1 1 100.00
edn_same_csr_outstanding 1.270s 47.831us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.580s 983.787us 1 1 100.00
edn_tl_intg_err 1.670s 252.277us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.950s 16.472us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.160s 305.815us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.580s 983.787us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.580s 983.787us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.580s 983.787us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.580s 983.787us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.160s 305.815us 1 1 100.00
edn_sec_cm 3.580s 983.787us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.160s 305.815us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.670s 252.277us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 86.210s 5334.707us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 111096377469366970241472022198334745977119228226773488105461422748597162392823 362
UVM_INFO @ 5334706700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---