Simulation Results: edn/edn1

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.03 %
  • code
  • 83.28 %
  • assert
  • 97.14 %
  • func
  • 80.67 %
  • line
  • 98.25 %
  • branch
  • 93.94 %
  • cond
  • 90.08 %
  • toggle
  • 87.55 %
  • FSM
  • 46.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.810s 40.159us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.850s 30.215us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.770s 25.441us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.150s 501.667us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.250s 134.593us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.190s 44.425us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.770s 25.441us 1 1 100.00
edn_csr_aliasing 1.250s 134.593us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.930s 62.321us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.930s 62.321us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.930s 62.321us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.890s 20.875us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.980s 23.945us 1 1 100.00
errs 1 1 100.00
edn_err 0.890s 63.090us 1 1 100.00
disable 2 2 100.00
edn_disable 0.720s 45.136us 1 1 100.00
edn_disable_auto_req_mode 1.000s 45.305us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.010s 128.295us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.700s 12.592us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.830s 33.461us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.460s 32.625us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.460s 32.625us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.850s 30.215us 1 1 100.00
edn_csr_rw 0.770s 25.441us 1 1 100.00
edn_csr_aliasing 1.250s 134.593us 1 1 100.00
edn_same_csr_outstanding 0.910s 41.164us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.850s 30.215us 1 1 100.00
edn_csr_rw 0.770s 25.441us 1 1 100.00
edn_csr_aliasing 1.250s 134.593us 1 1 100.00
edn_same_csr_outstanding 0.910s 41.164us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.570s 1643.793us 1 1 100.00
edn_tl_intg_err 1.250s 52.248us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.820s 16.272us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.980s 23.945us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.570s 1643.793us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.570s 1643.793us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.570s 1643.793us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.570s 1643.793us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.980s 23.945us 1 1 100.00
edn_sec_cm 3.570s 1643.793us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.980s 23.945us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.250s 52.248us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 6.480s 1052.191us 1 1 100.00