Simulation Results: flash_ctrl

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.33 %
  • code
  • 93.71 %
  • assert
  • 96.76 %
  • func
  • 95.51 %
  • line
  • 95.97 %
  • branch
  • 97.08 %
  • cond
  • 93.77 %
  • toggle
  • 98.04 %
  • FSM
  • 83.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
95.83%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 39.860s 85.951us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 18.920s 24.998us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 20.780s 205.858us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 6.450s 26.885us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 54.910s 9379.586us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 37.890s 1281.077us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 13.210s 366.066us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 6.450s 26.885us 1 1 100.00
flash_ctrl_csr_aliasing 37.890s 1281.077us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 5.580s 28.911us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.600s 19.532us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 13.430s 42.316us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 37.140s 126.554us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1273.380s 619395.940us 1 1 100.00
flash_ctrl_hw_rma_reset 517.050s 90150.566us 1 1 100.00
flash_ctrl_lcmgr_intg 9.210s 54.078us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1472.570s 234048.767us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 175.960s 5574.275us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 27.190s 390.949us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2916.980s 50873.345us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 94.030s 6442.328us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 17.170s 49.820us 1 1 100.00
flash_ctrl_rw_evict_all_en 18.710s 27.190us 1 1 100.00
flash_ctrl_re_evict 19.160s 144.332us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 83.020s 724.533us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 83.020s 724.533us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 152.560s 19372.272us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 15.710s 166.144us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 117.800s 55.833us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 396.560s 8468.817us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 253.910s 559.717us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 781.070s 741.892us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 8.850s 75.088us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 125.410s 2386.378us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.730s 44.042us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 5.110s 103.143us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 105.850s 200.839us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 129.000s 21631.289us 1 1 100.00
flash_ctrl_otp_reset 54.200s 41.556us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1273.380s 619395.940us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 141.420s 6883.030us 1 1 100.00
flash_ctrl_intr_wr 52.530s 11034.120us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 174.200s 25822.496us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 172.470s 227408.966us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 51.750s 1713.238us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 46.740s 6762.819us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 10.650s 251.692us 1 1 100.00
flash_ctrl_ro_derr 97.230s 1524.197us 1 1 100.00
flash_ctrl_rw_derr 137.260s 2077.830us 1 1 100.00
flash_ctrl_derr_detect 120.450s 3593.102us 1 1 100.00
flash_ctrl_integrity 462.140s 14213.700us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 10.090s 180.911us 1 1 100.00
flash_ctrl_ro_serr 85.810s 2426.814us 1 1 100.00
flash_ctrl_rw_serr 130.580s 5363.342us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 31.630s 6182.573us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 61.370s 982.065us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 106.430s 2459.149us 1 1 100.00
flash_ctrl_write_word_sweep 6.780s 154.009us 1 1 100.00
flash_ctrl_read_word_sweep 6.140s 88.332us 1 1 100.00
flash_ctrl_ro 87.890s 570.861us 1 1 100.00
flash_ctrl_rw 428.650s 11784.575us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 27.430s 1208.487us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 569.080s 43607.558us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 36.040s 10063.566us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 8.070s 64.600us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.370s 30.318us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 10.210s 210.858us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 10.210s 210.858us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 20.780s 205.858us 1 1 100.00
flash_ctrl_csr_rw 6.450s 26.885us 1 1 100.00
flash_ctrl_csr_aliasing 37.890s 1281.077us 1 1 100.00
flash_ctrl_same_csr_outstanding 13.500s 406.864us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 20.780s 205.858us 1 1 100.00
flash_ctrl_csr_rw 6.450s 26.885us 1 1 100.00
flash_ctrl_csr_aliasing 37.890s 1281.077us 1 1 100.00
flash_ctrl_same_csr_outstanding 13.500s 406.864us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 13.110s 44.516us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 13.110s 44.516us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 13.110s 44.516us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 13.110s 44.516us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 28.900s 288.817us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1553.000s 5140.379us 1 1 100.00
flash_ctrl_tl_intg_err 355.800s 1987.345us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 355.800s 1987.345us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 355.800s 1987.345us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 15.380s 383.284us 1 1 100.00
flash_ctrl_wr_intg 7.560s 196.541us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 39.860s 85.951us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 54.200s 41.556us 1 1 100.00
flash_ctrl_disable 10.730s 44.042us 1 1 100.00
flash_ctrl_sec_info_access 35.810s 7100.724us 1 1 100.00
flash_ctrl_connect 5.110s 103.143us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.640s 41.495us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.450s 26.885us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 13.110s 44.516us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.450s 26.885us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 13.110s 44.516us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.450s 26.885us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 13.110s 44.516us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.730s 44.042us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 15.380s 383.284us 1 1 100.00
flash_ctrl_access_after_disable 5.420s 40.192us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 13.740s 64.163us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.730s 44.042us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 15.710s 166.144us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 428.650s 11784.575us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 130.580s 5363.342us 1 1 100.00
flash_ctrl_rw_derr 137.260s 2077.830us 1 1 100.00
flash_ctrl_integrity 462.140s 14213.700us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1273.380s 619395.940us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1553.000s 5140.379us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1553.000s 5140.379us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1553.000s 5140.379us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1553.000s 5140.379us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 11.150s 814.465us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 0 1 0.00
flash_ctrl_phy_host_grant_err 5.900s 5.689us 0 1 0.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 9.960s 55.720us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1553.000s 5140.379us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1553.000s 5140.379us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1553.000s 5140.379us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 19.330s 168.600us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 185.280s 551.663us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
flash_ctrl_phy_host_grant_err 15403785063326221230548280394140143800535227794646253390019789354156418683235 125
UVM_ERROR @ 5689.5 ns: (alert_esc_if.sv:201) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 5689.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---