Simulation Results: hmac

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.14 %
  • code
  • 96.70 %
  • assert
  • 96.70 %
  • func
  • 44.02 %
  • line
  • 98.97 %
  • branch
  • 97.52 %
  • cond
  • 95.84 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 9.880s 4301.191us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.070s 130.038us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.910s 32.686us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.640s 2116.961us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.820s 620.669us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 0.940s 27.291us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.910s 32.686us 1 1 100.00
hmac_csr_aliasing 5.820s 620.669us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 29.840s 705.023us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 5.570s 121.828us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.360s 177.837us 1 1 100.00
hmac_test_sha384_vectors 399.640s 103761.288us 1 1 100.00
hmac_test_sha512_vectors 425.490s 272115.082us 1 1 100.00
hmac_test_hmac256_vectors 6.330s 372.319us 1 1 100.00
hmac_test_hmac384_vectors 10.150s 5028.022us 1 1 100.00
hmac_test_hmac512_vectors 7.920s 216.969us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 39.850s 4429.302us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 306.470s 4075.838us 1 1 100.00
error 1 1 100.00
hmac_error 8.130s 962.849us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 29.130s 890.344us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 9.880s 4301.191us 1 1 100.00
hmac_long_msg 29.840s 705.023us 1 1 100.00
hmac_back_pressure 5.570s 121.828us 1 1 100.00
hmac_datapath_stress 306.470s 4075.838us 1 1 100.00
hmac_burst_wr 39.850s 4429.302us 1 1 100.00
hmac_stress_all 563.450s 6964.413us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 9.880s 4301.191us 1 1 100.00
hmac_long_msg 29.840s 705.023us 1 1 100.00
hmac_back_pressure 5.570s 121.828us 1 1 100.00
hmac_datapath_stress 306.470s 4075.838us 1 1 100.00
hmac_wipe_secret 29.130s 890.344us 1 1 100.00
hmac_test_sha256_vectors 8.360s 177.837us 1 1 100.00
hmac_test_sha384_vectors 399.640s 103761.288us 1 1 100.00
hmac_test_sha512_vectors 425.490s 272115.082us 1 1 100.00
hmac_test_hmac256_vectors 6.330s 372.319us 1 1 100.00
hmac_test_hmac384_vectors 10.150s 5028.022us 1 1 100.00
hmac_test_hmac512_vectors 7.920s 216.969us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 9.880s 4301.191us 1 1 100.00
hmac_long_msg 29.840s 705.023us 1 1 100.00
hmac_back_pressure 5.570s 121.828us 1 1 100.00
hmac_datapath_stress 306.470s 4075.838us 1 1 100.00
hmac_burst_wr 39.850s 4429.302us 1 1 100.00
hmac_error 8.130s 962.849us 1 1 100.00
hmac_wipe_secret 29.130s 890.344us 1 1 100.00
hmac_test_sha256_vectors 8.360s 177.837us 1 1 100.00
hmac_test_sha384_vectors 399.640s 103761.288us 1 1 100.00
hmac_test_sha512_vectors 425.490s 272115.082us 1 1 100.00
hmac_test_hmac256_vectors 6.330s 372.319us 1 1 100.00
hmac_test_hmac384_vectors 10.150s 5028.022us 1 1 100.00
hmac_test_hmac512_vectors 7.920s 216.969us 1 1 100.00
hmac_stress_all 563.450s 6964.413us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 563.450s 6964.413us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.620s 13.936us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.720s 58.818us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.350s 213.811us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.350s 213.811us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.070s 130.038us 1 1 100.00
hmac_csr_rw 0.910s 32.686us 1 1 100.00
hmac_csr_aliasing 5.820s 620.669us 1 1 100.00
hmac_same_csr_outstanding 1.090s 39.970us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.070s 130.038us 1 1 100.00
hmac_csr_rw 0.910s 32.686us 1 1 100.00
hmac_csr_aliasing 5.820s 620.669us 1 1 100.00
hmac_same_csr_outstanding 1.090s 39.970us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.210s 65.201us 1 1 100.00
hmac_tl_intg_err 2.630s 367.992us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.630s 367.992us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 9.880s 4301.191us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.110s 85.420us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 85.380s 7920.910us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.970s 53.504us 1 1 100.00