Simulation Results

Simulation Results: i2c

22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
84.78 %

code
80.57 %

assert
95.98 %

func
77.80 %

line
95.92 %

branch
91.55 %

cond
84.25 %

toggle
89.45 %

FSM
41.67 %

Validation stages

V1		100.00%
V2		85.37%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	58.560s	3587.673us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	3.920s	827.989us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.720s	22.237us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.860s	153.348us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	2.510s	234.778us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.890s	177.094us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.020s	26.320us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.860s	153.348us	1	1	100.00
	i2c_csr_aliasing	1.890s	177.094us	1	1	100.00

35/41 passed

85.37 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.820s	124.130us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	210.970s	69778.100us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	356.000s	7421.592us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.690s	30.224us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	244.450s	20923.575us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	51.440s	10928.109us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.110s	133.403us	1	1	100.00
	i2c_host_fifo_fmt_empty	8.570s	1161.628us	1	1	100.00
	i2c_host_fifo_reset_rx	7.180s	208.843us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	81.110s	2254.266us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	11.120s	796.772us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.320s	96.089us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	3.060s	2367.810us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	17.870s	19003.185us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	2.710s	1965.924us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	8.350s	7235.188us	1	1	100.00
	i2c_target_intr_smoke	3.940s	1000.238us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.050s	279.606us	1	1	100.00
	i2c_target_fifo_reset_tx	0.840s	301.922us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	16.840s	11905.205us	1	1	100.00
	i2c_target_stress_rd	8.350s	7235.188us	1	1	100.00
	i2c_target_intr_stress_wr	2.920s	4947.792us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.910s	1431.415us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	6.120s	3223.445us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	2.880s	13102.622us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	12.180s	10507.162us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.440s	1783.344us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.190s	647.755us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	356.000s	7421.592us	1	1	100.00
	i2c_host_perf_precise	7.090s	2966.638us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	11.120s	796.772us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.440s	389.848us	1	1	100.00
target_mode_nack_generation				2	3	66.67
	i2c_target_nack_acqfull	2.290s	564.395us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.890s	1913.227us	1	1	100.00
	i2c_target_nack_txstretch	1.380s	183.703us	0	1	0.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	2.720s	226.551us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.530s	951.034us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.700s	38.884us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.720s	43.655us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.670s	110.868us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.670s	110.868us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.720s	22.237us	1	1	100.00
	i2c_csr_rw	0.860s	153.348us	1	1	100.00
	i2c_csr_aliasing	1.890s	177.094us	1	1	100.00
	i2c_same_csr_outstanding	2.500s	2641.622us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.720s	22.237us	1	1	100.00
	i2c_csr_rw	0.860s	153.348us	1	1	100.00
	i2c_csr_aliasing	1.890s	177.094us	1	1	100.00
	i2c_same_csr_outstanding	2.500s	2641.622us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.240s	324.695us	1	1	100.00
	i2c_sec_cm	0.910s	69.751us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.240s	324.695us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	4.270s	570.865us	1
target_error_intr				1
	i2c_target_unexp_stop	0.790s	402.948us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	10.510s	19621.116us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
	i2c_host_error_intr	18556905762868948630154614970129719600396288372218241188067950380323076976492	80	UVM_INFO @ 124130493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	112233826830356999935868440151114548705758810021792256219213779890780347757091	104	UVM_INFO @ 69778099970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	32110531857174413337830111695736275987734874306210410307731606814476206287169	96	UVM_INFO @ 19621115555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	i2c_target_glitch	67727773170068191625666965282730112606846903451948965691789472386042204677477	84	UVM_INFO @ 2367810486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])
	i2c_target_unexp_stop	56243810959012256692087099168754411405561877164481640160251992848335662465506	78	UVM_INFO @ 402947979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
	i2c_target_hrst	103571974621702002811372369210399158613383843380372957879966184303683015611193	79	UVM_INFO @ 10507161863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	i2c_host_stress_all_with_rand_reset	64514828089132179489482811648068377851043135012423116742400199856552750607184	102	UVM_INFO @ 570865467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
	i2c_host_mode_toggle	113260792792387245766020455474905530912224500782385557136761035643063706913256	87	--> EXP: --------------------------------------------------- Name Type Size Value ---------------------------------------------------
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: i2c_reg_block.target_nack_count reset value:
	i2c_target_nack_txstretch	93657996409723629723049417486693803400926655542851572043943487564761318971923	78	UVM_INFO @ 183702658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---