Simulation Results: keymgr

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.69 %
  • code
  • 96.53 %
  • assert
  • 97.72 %
  • func
  • 65.82 %
  • line
  • 98.92 %
  • branch
  • 97.99 %
  • cond
  • 92.64 %
  • toggle
  • 97.74 %
  • FSM
  • 95.35 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 3.130s 154.110us 1 1 100.00
random 1 1 100.00
keymgr_random 2.500s 133.335us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.100s 156.943us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.020s 87.814us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 18.100s 3734.887us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 4.770s 1516.627us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.300s 166.468us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.020s 87.814us 1 1 100.00
keymgr_csr_aliasing 4.770s 1516.627us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 1.830s 282.641us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 4.510s 258.000us 1 1 100.00
keymgr_sideload_kmac 14.220s 1456.022us 1 1 100.00
keymgr_sideload_aes 2.770s 238.289us 1 1 100.00
keymgr_sideload_otbn 2.150s 125.870us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 1.220s 37.958us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 2.490s 77.691us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 4.700s 330.841us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 2.860s 87.709us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 1.690s 24.449us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.890s 158.917us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 34.930s 5148.094us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.750s 22.376us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 1.580s 49.415us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 1.980s 516.707us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 1.980s 516.707us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.100s 156.943us 1 1 100.00
keymgr_csr_rw 1.020s 87.814us 1 1 100.00
keymgr_csr_aliasing 4.770s 1516.627us 1 1 100.00
keymgr_same_csr_outstanding 1.610s 35.561us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.100s 156.943us 1 1 100.00
keymgr_csr_rw 1.020s 87.814us 1 1 100.00
keymgr_csr_aliasing 4.770s 1516.627us 1 1 100.00
keymgr_same_csr_outstanding 1.610s 35.561us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 4.870s 476.193us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 4.870s 476.193us 1 1 100.00
keymgr_tl_intg_err 5.180s 513.674us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 4.850s 855.539us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 4.850s 855.539us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 4.850s 855.539us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 4.850s 855.539us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 7.090s 1440.684us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 4.870s 476.193us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 4.870s 476.193us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 5.180s 513.674us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 4.850s 855.539us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 1.830s 282.641us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 2.500s 133.335us 1 1 100.00
keymgr_csr_rw 1.020s 87.814us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 2.500s 133.335us 1 1 100.00
keymgr_csr_rw 1.020s 87.814us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 2.500s 133.335us 1 1 100.00
keymgr_csr_rw 1.020s 87.814us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 2.490s 77.691us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.690s 24.449us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.690s 24.449us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 2.500s 133.335us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 2.260s 66.204us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.870s 476.193us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.870s 476.193us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 4.870s 476.193us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 3.170s 81.068us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 2.490s 77.691us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 4.870s 476.193us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.870s 476.193us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 4.870s 476.193us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.170s 81.068us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.170s 81.068us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 4.870s 476.193us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.170s 81.068us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.870s 476.193us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 3.170s 81.068us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 3.310s 421.717us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 69213399546542776398424180615154625782346280610994706555963097193844798757080 127
UVM_INFO @ 421717495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---