Simulation Results: lc_ctrl/volatile_unlock_disabled

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.61 %
  • code
  • 84.38 %
  • assert
  • 93.85 %
  • func
  • 93.59 %
  • line
  • 97.21 %
  • branch
  • 93.97 %
  • cond
  • 79.17 %
  • toggle
  • 88.00 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 5.280s 859.720us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.210s 17.440us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.820s 20.536us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.680s 233.832us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 53.815us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.410s 28.565us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.820s 20.536us 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 53.815us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.460s 273.978us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 12.740s 942.855us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.950s 33.054us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 5.520s 271.574us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.240s 201.549us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.080s 343.955us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.240s 201.549us 1 1 100.00
lc_ctrl_prog_failure 5.520s 271.574us 1 1 100.00
lc_ctrl_errors 7.080s 343.955us 1 1 100.00
lc_ctrl_security_escalation 7.470s 317.699us 1 1 100.00
lc_ctrl_jtag_state_failure 22.150s 6624.769us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.080s 1105.662us 1 1 100.00
lc_ctrl_jtag_errors 47.350s 2446.189us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 5.430s 911.937us 1 1 100.00
lc_ctrl_jtag_state_post_trans 16.690s 1643.161us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.080s 1105.662us 1 1 100.00
lc_ctrl_jtag_errors 47.350s 2446.189us 1 1 100.00
lc_ctrl_jtag_access 1.640s 182.880us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 14.400s 5051.354us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.710s 542.177us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.210s 205.731us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.750s 480.267us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 9.200s 6579.110us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.130s 29.686us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.590s 318.790us 1 1 100.00
lc_ctrl_jtag_alert_test 1.940s 228.751us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 8.230s 1634.754us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.910s 14.767us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 54.810s 24021.102us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.960s 20.689us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.350s 211.063us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.350s 211.063us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.210s 17.440us 1 1 100.00
lc_ctrl_csr_rw 0.820s 20.536us 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 53.815us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.230s 126.014us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.210s 17.440us 1 1 100.00
lc_ctrl_csr_rw 0.820s 20.536us 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 53.815us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.230s 126.014us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.710s 165.169us 1 1 100.00
lc_ctrl_tl_intg_err 3.190s 181.789us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.190s 181.789us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 12.740s 942.855us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.240s 201.549us 1 1 100.00
lc_ctrl_sec_cm 7.710s 165.169us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.240s 201.549us 1 1 100.00
lc_ctrl_sec_cm 7.710s 165.169us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.240s 201.549us 1 1 100.00
lc_ctrl_sec_cm 7.710s 165.169us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.240s 201.549us 1 1 100.00
lc_ctrl_sec_cm 7.710s 165.169us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.240s 201.549us 1 1 100.00
lc_ctrl_sec_cm 7.710s 165.169us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.240s 201.549us 1 1 100.00
lc_ctrl_sec_cm 7.710s 165.169us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.240s 201.549us 1 1 100.00
lc_ctrl_sec_cm 7.710s 165.169us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.240s 201.549us 1 1 100.00
lc_ctrl_sec_cm 7.710s 165.169us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.470s 317.699us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.460s 273.978us 1 1 100.00
lc_ctrl_jtag_state_post_trans 16.690s 1643.161us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.410s 3204.768us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.410s 3204.768us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.260s 1560.135us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.850s 1316.282us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.850s 1316.282us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 21.660s 3350.813us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 41700637967454407461145979435247517944249868565598570568785167730799320095572 1751
UVM_INFO @ 3350812560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---