Simulation Results: lc_ctrl/volatile_unlock_enabled

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.60 %
  • code
  • 84.42 %
  • assert
  • 94.13 %
  • func
  • 93.24 %
  • line
  • 97.19 %
  • branch
  • 93.62 %
  • cond
  • 79.49 %
  • toggle
  • 88.26 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.030s 15.853us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.040s 19.509us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.070s 20.845us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.330s 135.037us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 17.261us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.440s 60.769us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.070s 20.845us 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 17.261us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.940s 103.078us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 13.360s 558.908us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.780s 20.442us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.320s 36.098us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.440s 256.650us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.410s 1255.181us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.440s 256.650us 1 1 100.00
lc_ctrl_prog_failure 1.320s 36.098us 1 1 100.00
lc_ctrl_errors 6.410s 1255.181us 1 1 100.00
lc_ctrl_security_escalation 5.310s 976.814us 1 1 100.00
lc_ctrl_jtag_state_failure 22.750s 1439.728us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.050s 590.129us 1 1 100.00
lc_ctrl_jtag_errors 54.280s 17306.234us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.640s 462.310us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.850s 2704.738us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.050s 590.129us 1 1 100.00
lc_ctrl_jtag_errors 54.280s 17306.234us 1 1 100.00
lc_ctrl_jtag_access 2.040s 198.305us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 21.450s 949.077us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.360s 403.724us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.410s 177.226us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 31.810s 4085.887us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.300s 185.848us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.700s 138.051us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.860s 156.790us 1 1 100.00
lc_ctrl_jtag_alert_test 1.950s 147.075us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.090s 2321.559us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.900s 22.970us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 47.020s 5741.985us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.900s 85.685us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.490s 123.549us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.490s 123.549us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.040s 19.509us 1 1 100.00
lc_ctrl_csr_rw 1.070s 20.845us 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 17.261us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.320s 28.724us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.040s 19.509us 1 1 100.00
lc_ctrl_csr_rw 1.070s 20.845us 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 17.261us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.320s 28.724us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 10.430s 220.913us 1 1 100.00
lc_ctrl_tl_intg_err 1.420s 928.665us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.420s 928.665us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 13.360s 558.908us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.440s 256.650us 1 1 100.00
lc_ctrl_sec_cm 10.430s 220.913us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.440s 256.650us 1 1 100.00
lc_ctrl_sec_cm 10.430s 220.913us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.440s 256.650us 1 1 100.00
lc_ctrl_sec_cm 10.430s 220.913us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.440s 256.650us 1 1 100.00
lc_ctrl_sec_cm 10.430s 220.913us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.440s 256.650us 1 1 100.00
lc_ctrl_sec_cm 10.430s 220.913us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.440s 256.650us 1 1 100.00
lc_ctrl_sec_cm 10.430s 220.913us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.440s 256.650us 1 1 100.00
lc_ctrl_sec_cm 10.430s 220.913us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.440s 256.650us 1 1 100.00
lc_ctrl_sec_cm 10.430s 220.913us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.310s 976.814us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.940s 103.078us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.850s 2704.738us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 12.940s 524.295us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 12.940s 524.295us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 11.680s 934.645us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.540s 1097.934us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.540s 1097.934us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 3.570s 2584.665us 1 1 100.00