Simulation Results: otbn

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.64 %
  • code
  • 95.33 %
  • assert
  • 89.88 %
  • func
  • 98.73 %
  • block
  • 99.41 %
  • line
  • 99.58 %
  • branch
  • 92.56 %
  • toggle
  • 91.72 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
92.86%
V2S
92.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 19.000s 93.466us 1 1 100.00
single_binary 1 1 100.00
otbn_single 5.000s 52.300us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 29.000s 56.196us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 28.000s 11.567us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 30.000s 69.024us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 29.000s 17.864us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 30.000s 619.303us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 28.000s 11.567us 1 1 100.00
otbn_csr_aliasing 29.000s 17.864us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 53.000s 4652.947us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 21.000s 178.064us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 21.000s 66.567us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 48.000s 127.980us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 19.000s 307.814us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 9.000s 35.372us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 28.000s 537.394us 1 1 100.00
zero_state_err_urnd 0 1 0.00
otbn_zero_state_err_urnd 6.000s 10.839us 0 1 0.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 6.000s 18.337us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 29.000s 85.164us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 87.813us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 164.700us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 164.700us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 29.000s 56.196us 1 1 100.00
otbn_csr_rw 28.000s 11.567us 1 1 100.00
otbn_csr_aliasing 29.000s 17.864us 1 1 100.00
otbn_same_csr_outstanding 4.000s 48.150us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 29.000s 56.196us 1 1 100.00
otbn_csr_rw 28.000s 11.567us 1 1 100.00
otbn_csr_aliasing 29.000s 17.864us 1 1 100.00
otbn_same_csr_outstanding 4.000s 48.150us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 22.000s 25.930us 1 1 100.00
otbn_dmem_err 34.000s 22.097us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 39.000s 89.483us 1 1 100.00
otbn_controller_ispr_rdata_err 33.000s 59.713us 1 1 100.00
otbn_mac_bignum_acc_err 6.000s 96.749us 1 1 100.00
otbn_urnd_err 8.000s 10.160us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 24.000s 16.724us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 5.000s 12.533us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 16.034us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 164.000s 3940.781us 1 1 100.00
otbn_tl_intg_err 74.000s 572.818us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 37.000s 208.916us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 164.000s 3940.781us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 164.000s 3940.781us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 19.000s 93.466us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 34.000s 22.097us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 22.000s 25.930us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 74.000s 572.818us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 28.000s 537.394us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 22.000s 25.930us 1 1 100.00
otbn_dmem_err 34.000s 22.097us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 10.839us 0 1 0.00
otbn_illegal_mem_acc 24.000s 16.724us 1 1 100.00
otbn_sec_cm 164.000s 3940.781us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 164.000s 3940.781us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 5.000s 52.300us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 22.000s 25.930us 1 1 100.00
otbn_dmem_err 34.000s 22.097us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 10.839us 0 1 0.00
otbn_illegal_mem_acc 24.000s 16.724us 1 1 100.00
otbn_sec_cm 164.000s 3940.781us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 164.000s 3940.781us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 28.000s 537.394us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 22.000s 25.930us 1 1 100.00
otbn_dmem_err 34.000s 22.097us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 10.839us 0 1 0.00
otbn_illegal_mem_acc 24.000s 16.724us 1 1 100.00
otbn_sec_cm 164.000s 3940.781us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 164.000s 3940.781us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 5.000s 52.300us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 30.000s 33.670us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 5.000s 60.562us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 21.000s 340.919us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 21.000s 340.919us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 5.000s 42.126us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 164.000s 3940.781us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 164.000s 3940.781us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 9.000s 56.043us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 164.000s 3940.781us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 164.000s 3940.781us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 13.000s 44.016us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 13.000s 44.016us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 37.884us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 5.000s 52.300us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 5.000s 52.300us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 5.000s 52.300us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 19.000s 307.814us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 5.000s 52.300us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 5.000s 52.300us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 18.000s 214.517us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 5.000s 52.300us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 164.000s 3940.781us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 181.000s 1705.364us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 6.000s 36.943us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_zero_state_err_urnd 23900221005899592993498784811560448435258294571775675021743597502894262948555 107
UVM_INFO @ 10838767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_urnd_err 50046013855444617735089927359416279464750694989871967287575691152815608069211 110
UVM_INFO @ 10160022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---