Simulation Results: pattgen

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
81.82%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 2.000s 126.341us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 46.601us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 13.287us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 2.000s 133.619us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 2.000s 27.935us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 105.066us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 13.287us 1 1 100.00
pattgen_csr_aliasing 2.000s 27.935us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 0 1 0.00
pattgen_perf 773.000s 600000.000us 0 1 0.00
cnt_rollover 1 1 100.00
cnt_rollover 32.000s 10032.999us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 71.358us 1 1 100.00
stress_all 0 1 0.00
pattgen_stress_all 92.000s 8504.713us 0 1 0.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 13.358us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 24.993us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 1.000s 388.473us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 1.000s 388.473us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 46.601us 1 1 100.00
pattgen_csr_rw 1.000s 13.287us 1 1 100.00
pattgen_csr_aliasing 2.000s 27.935us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 30.218us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 46.601us 1 1 100.00
pattgen_csr_rw 1.000s 13.287us 1 1 100.00
pattgen_csr_aliasing 2.000s 27.935us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 30.218us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_tl_intg_err 1.000s 52.884us 1 1 100.00
pattgen_sec_cm 1.000s 104.587us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 1.000s 52.884us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 8.000s 2070.080us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 1.000s 64.404us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
pattgen_perf 61576366378250035439292201901862975334482023897836338854907273560110538655723 99
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
pattgen_stress_all_with_rand_reset 55118492768259157778527105969034204356593485530404189850856658588329262215933 232
UVM_ERROR @ 2008040829 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2008040829 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 2008260339 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared:
pattgen_stress_all 75966336422830876737809351805097518800923840064910450649828070005867818479226 153
----------------------------------------
Name Type Size Value
----------------------------------------
exp_item pattgen_item - @10301