Simulation Results: pwrmgr

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.69 %
  • code
  • 94.60 %
  • assert
  • 96.08 %
  • func
  • 96.38 %
  • line
  • 98.92 %
  • branch
  • 95.42 %
  • cond
  • 94.63 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.650s 37.804us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.740s 24.816us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.620s 19.398us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.570s 163.263us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.760s 183.046us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.350s 77.097us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.620s 19.398us 1 1 100.00
pwrmgr_csr_aliasing 0.760s 183.046us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.690s 71.254us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.690s 71.254us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.920s 79.879us 1 1 100.00
pwrmgr_lowpower_invalid 0.700s 111.716us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.800s 76.631us 1 1 100.00
pwrmgr_reset_invalid 0.850s 107.924us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.800s 76.631us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.670s 109.505us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 1.060s 224.548us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 1.100s 147.614us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 3.560s 1656.750us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.590s 17.398us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.730s 486.404us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.730s 486.404us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.740s 24.816us 1 1 100.00
pwrmgr_csr_rw 0.620s 19.398us 1 1 100.00
pwrmgr_csr_aliasing 0.760s 183.046us 1 1 100.00
pwrmgr_same_csr_outstanding 0.820s 538.574us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.740s 24.816us 1 1 100.00
pwrmgr_csr_rw 0.620s 19.398us 1 1 100.00
pwrmgr_csr_aliasing 0.760s 183.046us 1 1 100.00
pwrmgr_same_csr_outstanding 0.820s 538.574us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 0.640s 7.545us 0 1 0.00
pwrmgr_sec_cm 0.720s 21.159us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.720s 21.159us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.720s 21.159us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.640s 7.545us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.400s 1056.414us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.670s 109.505us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.720s 51.945us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.630s 37.038us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.720s 21.159us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.720s 21.159us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.720s 21.159us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.640s 50.762us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.610s 36.176us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.870s 154.152us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.620s 19.398us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.620s 19.398us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.750s 370.445us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 4.290s 1496.727us 1 1 100.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)'
pwrmgr_escalation_timeout 22477489187263699474063693621483597474664080444277185264111711697513578684773 79
UVM_ERROR @ 370444954 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 370444954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire
pwrmgr_tl_intg_err 97837288426565959173757717105914424541605258910815695615891508961176912219826 82
UVM_INFO @ 7545054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 17664337519212464596572216048294418701473498445916135744278736582786583881174 84
UVM_INFO @ 21158780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---