Simulation Results: rom_ctrl/32kb

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.29 %
  • code
  • 92.78 %
  • assert
  • 96.66 %
  • func
  • 96.42 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 95.10 %
  • toggle
  • 96.74 %
  • FSM
  • 73.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.590s 141.376us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 6.110s 214.780us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.560s 126.436us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.770s 1031.945us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.410s 207.499us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.210s 1071.201us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.560s 126.436us 1 1 100.00
rom_ctrl_csr_aliasing 3.410s 207.499us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.260s 211.984us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.290s 169.461us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.550s 142.728us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 10.050s 346.866us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 5.900s 1088.567us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.390s 400.781us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.510s 171.733us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.510s 171.733us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.110s 214.780us 1 1 100.00
rom_ctrl_csr_rw 3.560s 126.436us 1 1 100.00
rom_ctrl_csr_aliasing 3.410s 207.499us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.550s 557.634us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.110s 214.780us 1 1 100.00
rom_ctrl_csr_rw 3.560s 126.436us 1 1 100.00
rom_ctrl_csr_aliasing 3.410s 207.499us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.550s 557.634us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 59.340s 3098.697us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 10.980s 1022.905us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 195.150s 1180.374us 1 1 100.00
rom_ctrl_tl_intg_err 24.350s 285.483us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 195.150s 1180.374us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 195.150s 1180.374us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 59.340s 3098.697us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 59.340s 3098.697us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 59.340s 3098.697us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 59.340s 3098.697us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 59.340s 3098.697us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 195.150s 1180.374us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 195.150s 1180.374us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.590s 141.376us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.590s 141.376us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.590s 141.376us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 24.350s 285.483us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 59.340s 3098.697us 0 1 0.00
rom_ctrl_kmac_err_chk 5.900s 1088.567us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 59.340s 3098.697us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 59.340s 3098.697us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 59.340s 3098.697us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 10.980s 1022.905us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 195.150s 1180.374us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 24.140s 2826.863us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
rom_ctrl_corrupt_sig_fatal_chk 63311977759525596955694911307343281808172129666687925529766898959196422525648 105
UVM_INFO @ 3098696597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---