Simulation Results: rom_ctrl/64kb

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.81 %
  • code
  • 99.50 %
  • assert
  • 96.80 %
  • func
  • 97.14 %
  • line
  • 99.59 %
  • branch
  • 99.64 %
  • cond
  • 98.66 %
  • toggle
  • 99.59 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.400s 1117.721us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 9.200s 295.151us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.000s 726.039us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 8.640s 840.321us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.570s 650.522us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.540s 265.518us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.000s 726.039us 1 1 100.00
rom_ctrl_csr_aliasing 5.570s 650.522us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 8.170s 302.183us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.960s 301.366us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 8.720s 1106.886us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 25.670s 756.946us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 18.290s 7612.843us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 5.680s 699.082us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.940s 301.658us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.940s 301.658us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.200s 295.151us 1 1 100.00
rom_ctrl_csr_rw 6.000s 726.039us 1 1 100.00
rom_ctrl_csr_aliasing 5.570s 650.522us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.130s 298.187us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.200s 295.151us 1 1 100.00
rom_ctrl_csr_rw 6.000s 726.039us 1 1 100.00
rom_ctrl_csr_aliasing 5.570s 650.522us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.130s 298.187us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 127.770s 3385.175us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.890s 3135.392us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 230.470s 903.763us 1 1 100.00
rom_ctrl_tl_intg_err 95.000s 1812.042us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 230.470s 903.763us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 230.470s 903.763us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 127.770s 3385.175us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 127.770s 3385.175us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 127.770s 3385.175us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 127.770s 3385.175us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 127.770s 3385.175us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 230.470s 903.763us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 230.470s 903.763us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.400s 1117.721us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.400s 1117.721us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.400s 1117.721us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 95.000s 1812.042us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 127.770s 3385.175us 1 1 100.00
rom_ctrl_kmac_err_chk 18.290s 7612.843us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 127.770s 3385.175us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 127.770s 3385.175us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 127.770s 3385.175us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.890s 3135.392us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 230.470s 903.763us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 81.100s 4842.777us 1 1 100.00