Simulation Results: rstmgr

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.53 %
  • code
  • 99.33 %
  • assert
  • 97.99 %
  • func
  • 95.27 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.82 %
  • toggle
  • 99.16 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.060s 124.856us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.850s 153.863us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.740s 80.946us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.250s 489.659us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.600s 208.731us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.460s 170.450us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.740s 80.946us 1 1 100.00
rstmgr_csr_aliasing 1.600s 208.731us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.930s 241.779us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.600s 145.149us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.390s 276.275us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.100s 1399.628us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.100s 1399.628us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.100s 1399.628us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.100s 1399.628us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 4.650s 1831.626us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.890s 62.605us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.080s 386.534us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.080s 386.534us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.850s 153.863us 1 1 100.00
rstmgr_csr_rw 0.740s 80.946us 1 1 100.00
rstmgr_csr_aliasing 1.600s 208.731us 1 1 100.00
rstmgr_same_csr_outstanding 1.010s 105.707us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.850s 153.863us 1 1 100.00
rstmgr_csr_rw 0.740s 80.946us 1 1 100.00
rstmgr_csr_aliasing 1.600s 208.731us 1 1 100.00
rstmgr_same_csr_outstanding 1.010s 105.707us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 19.050s 16987.337us 1 1 100.00
rstmgr_tl_intg_err 2.390s 791.658us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 19.050s 16987.337us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 19.050s 16987.337us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.390s 791.658us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.040s 170.541us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 5.950s 2256.294us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.190s 301.780us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 19.050s 16987.337us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.740s 80.946us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.740s 80.946us 1 1 100.00