Simulation Results: rv_timer

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.57 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 95.88 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.610s 101.797us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.580s 224.886us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.680s 26.126us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.200s 98.571us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.830s 103.222us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.710s 29.001us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.680s 26.126us 1 1 100.00
rv_timer_csr_aliasing 0.830s 103.222us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.680s 291.371us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.440s 789.331us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 292.080s 239677.634us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 292.080s 239677.634us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.070s 3594.824us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.570s 43.181us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.730s 21.326us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.770s 896.958us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.770s 896.958us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.580s 224.886us 1 1 100.00
rv_timer_csr_rw 0.680s 26.126us 1 1 100.00
rv_timer_csr_aliasing 0.830s 103.222us 1 1 100.00
rv_timer_same_csr_outstanding 0.740s 25.237us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.580s 224.886us 1 1 100.00
rv_timer_csr_rw 0.680s 26.126us 1 1 100.00
rv_timer_csr_aliasing 0.830s 103.222us 1 1 100.00
rv_timer_same_csr_outstanding 0.740s 25.237us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.870s 67.357us 1 1 100.00
rv_timer_tl_intg_err 1.200s 430.016us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.200s 430.016us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.590s 27.221us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 0.600s 45.499us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 17.170s 12664.708us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 77959867717380933993741972751572712274442639890206940606002582225414940338131 75
UVM_INFO @ 45498817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_random_reset 108953813744550480793266484971966015227549206510458412229584713675079442239132 75
UVM_INFO @ 291370929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---