Simulation Results: spi_device/1r1w

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.10 %
  • code
  • 93.15 %
  • assert
  • 94.64 %
  • func
  • 73.51 %
  • line
  • 99.07 %
  • branch
  • 98.33 %
  • cond
  • 95.44 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 384.770s 288477.500us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.090s 199.355us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.110s 39.120us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 26.120s 16336.381us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 10.050s 743.176us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.440s 390.153us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.110s 39.120us 1 1 100.00
spi_device_csr_aliasing 10.050s 743.176us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.780s 17.295us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.100s 127.888us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.740s 19.462us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.770s 6.158us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.880s 3.730us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.310s 1291.807us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.310s 1291.807us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 1.690s 799.679us 1 1 100.00
spi_device_tpm_sts_read 0.970s 974.224us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 3.970s 2667.423us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 5.120s 1017.903us 1 1 100.00
spi_device_flash_all 28.930s 8735.181us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 10.720s 6220.458us 1 1 100.00
spi_device_flash_all 28.930s 8735.181us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 10.720s 6220.458us 1 1 100.00
spi_device_flash_all 28.930s 8735.181us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 28.930s 8735.181us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 1.930s 65.591us 1 1 100.00
spi_device_flash_all 28.930s 8735.181us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 1.930s 65.591us 1 1 100.00
spi_device_flash_all 28.930s 8735.181us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 1.930s 65.591us 1 1 100.00
spi_device_flash_all 28.930s 8735.181us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 1.930s 65.591us 1 1 100.00
spi_device_flash_all 28.930s 8735.181us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 1.930s 65.591us 1 1 100.00
spi_device_flash_all 28.930s 8735.181us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.890s 468.332us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 24.200s 110780.503us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 24.200s 110780.503us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 24.200s 110780.503us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 3.390s 404.158us 1 1 100.00
spi_device_read_buffer_direct 3.320s 109.109us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 24.200s 110780.503us 1 1 100.00
spi_device_flash_all 28.930s 8735.181us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 28.930s 8735.181us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 28.930s 8735.181us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.520s 109.514us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.520s 109.514us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 384.770s 288477.500us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 50.030s 5708.856us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 234.800s 99077.776us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.690s 14.005us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.770s 44.393us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.360s 174.463us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.360s 174.463us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.090s 199.355us 1 1 100.00
spi_device_csr_rw 2.110s 39.120us 1 1 100.00
spi_device_csr_aliasing 10.050s 743.176us 1 1 100.00
spi_device_same_csr_outstanding 2.870s 883.489us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.090s 199.355us 1 1 100.00
spi_device_csr_rw 2.110s 39.120us 1 1 100.00
spi_device_csr_aliasing 10.050s 743.176us 1 1 100.00
spi_device_same_csr_outstanding 2.870s 883.489us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.950s 129.470us 1 1 100.00
spi_device_tl_intg_err 6.320s 386.462us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 6.320s 386.462us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 62.950s 26952.565us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
spi_device_mem_parity 79747693774116787318802669203983278157043143164996348234840045723125595114455 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 3449578 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 3449578 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[938])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])
spi_device_ram_cfg 103925307365002338407262930638866957157262955887594156982305671167928737889301 76
UVM_ERROR @ 984407 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe418f [11100100000110001111] vs 0x0 [0])
UVM_ERROR @ 1078407 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x40efc0 [10000001110111111000000] vs 0x0 [0])
UVM_ERROR @ 1153407 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbf3 [101111110011] vs 0x0 [0])
UVM_ERROR @ 1185407 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2ca93 [101100101010010011] vs 0x0 [0])