Simulation Results: spi_device/2p

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.75 %
  • code
  • 94.15 %
  • assert
  • 94.49 %
  • func
  • 68.60 %
  • line
  • 99.13 %
  • branch
  • 98.42 %
  • cond
  • 96.08 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 3.330s 586.115us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.040s 137.843us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.370s 40.722us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 16.040s 1452.827us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 5.460s 432.242us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.820s 120.912us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.370s 40.722us 1 1 100.00
spi_device_csr_aliasing 5.460s 432.242us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.780s 11.022us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.040s 597.832us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.830s 30.357us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 1.040s 15.416us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.860s 35.834us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.080s 42.998us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.080s 42.998us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 16.330s 15854.162us 1 1 100.00
spi_device_tpm_sts_read 1.040s 71.442us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 2.230s 376.651us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 7.950s 3480.575us 1 1 100.00
spi_device_flash_all 120.550s 102045.785us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 9.540s 24610.711us 1 1 100.00
spi_device_flash_all 120.550s 102045.785us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 9.540s 24610.711us 1 1 100.00
spi_device_flash_all 120.550s 102045.785us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 120.550s 102045.785us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.160s 3170.662us 1 1 100.00
spi_device_flash_all 120.550s 102045.785us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.160s 3170.662us 1 1 100.00
spi_device_flash_all 120.550s 102045.785us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.160s 3170.662us 1 1 100.00
spi_device_flash_all 120.550s 102045.785us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.160s 3170.662us 1 1 100.00
spi_device_flash_all 120.550s 102045.785us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.160s 3170.662us 1 1 100.00
spi_device_flash_all 120.550s 102045.785us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 11.430s 3837.950us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 8.320s 2270.061us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 8.320s 2270.061us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 8.320s 2270.061us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 26.400s 5151.352us 1 1 100.00
spi_device_read_buffer_direct 3.040s 224.322us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 8.320s 2270.061us 1 1 100.00
spi_device_flash_all 120.550s 102045.785us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 120.550s 102045.785us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 120.550s 102045.785us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 7.900s 22746.294us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 7.900s 22746.294us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 3.330s 586.115us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 84.510s 25576.226us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 86.310s 19558.132us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.840s 53.347us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.850s 30.205us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.070s 88.676us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.070s 88.676us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.040s 137.843us 1 1 100.00
spi_device_csr_rw 1.370s 40.722us 1 1 100.00
spi_device_csr_aliasing 5.460s 432.242us 1 1 100.00
spi_device_same_csr_outstanding 3.850s 745.456us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.040s 137.843us 1 1 100.00
spi_device_csr_rw 1.370s 40.722us 1 1 100.00
spi_device_csr_aliasing 5.460s 432.242us 1 1 100.00
spi_device_same_csr_outstanding 3.850s 745.456us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.450s 377.036us 1 1 100.00
spi_device_tl_intg_err 6.110s 1079.834us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 6.110s 1079.834us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 26.210s 17841.643us 1 1 100.00