Simulation Results: spi_host

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.75 %
  • code
  • 95.03 %
  • assert
  • 94.13 %
  • func
  • 89.08 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 43.000s 2700.587us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 25.818us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 18.486us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 60.012us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 41.822us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 308.972us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 18.486us 1 1 100.00
spi_host_csr_aliasing 1.000s 41.822us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 21.558us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 15.572us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 20.026us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 56.696us 1 1 100.00
spi_host_error_cmd 1.000s 19.348us 1 1 100.00
spi_host_event 10.000s 1090.932us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 1.000s 33.937us 1 1 100.00
speed 1 1 100.00
spi_host_speed 1.000s 33.937us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 1.000s 33.937us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 4.000s 203.224us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 72.707us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 1.000s 33.937us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 1.000s 33.937us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 43.000s 2700.587us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 43.000s 2700.587us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 81.000s 13210.186us 1 1 100.00
spien 1 1 100.00
spi_host_spien 5.000s 206.448us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 84.000s 2822.543us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 329.672us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 56.696us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 63.620us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 17.195us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 135.507us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 135.507us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 25.818us 1 1 100.00
spi_host_csr_rw 1.000s 18.486us 1 1 100.00
spi_host_csr_aliasing 1.000s 41.822us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 99.447us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 25.818us 1 1 100.00
spi_host_csr_rw 1.000s 18.486us 1 1 100.00
spi_host_csr_aliasing 1.000s 41.822us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 99.447us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 94.491us 1 1 100.00
spi_host_sec_cm 1.000s 73.734us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 94.491us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 275.000s 26696.994us 1 1 100.00