Simulation Results: sram_ctrl/main

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.50 %
  • code
  • 96.79 %
  • assert
  • 96.32 %
  • func
  • 93.40 %
  • block
  • 96.15 %
  • line
  • 96.88 %
  • branch
  • 94.33 %
  • toggle
  • 95.94 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 379.202us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 44.342us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 11.278us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 98.441us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 25.211us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 1655.006us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 11.278us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 25.211us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 219.000s 21121.912us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 54.000s 10878.169us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 24.000s 4526.925us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 109.000s 3190.194us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 160.000s 282279.981us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 41.000s 44360.945us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 56.000s 16986.057us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 14.000s 5705.328us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 406.331us 1 1 100.00
sram_ctrl_partial_access_b2b 175.000s 49765.493us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 3.000s 673.365us 1 1 100.00
sram_ctrl_throughput_w_partial_write 5.000s 2669.686us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 6098.634us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 7.000s 4766.716us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 1993.324us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 247.000s 25015.101us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 54.030us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 41.051us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 41.051us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 44.342us 1 1 100.00
sram_ctrl_csr_rw 2.000s 11.278us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 25.211us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 25.271us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 44.342us 1 1 100.00
sram_ctrl_csr_rw 2.000s 11.278us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 25.211us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 25.271us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 11.000s 3854.162us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 415.645us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 1926.385us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 415.645us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 1926.385us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 4766.716us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 4766.716us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 11.278us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 14.000s 5705.328us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 14.000s 5705.328us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 14.000s 5705.328us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 56.000s 16986.057us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 2023.535us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 11.000s 3854.162us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.000s 709.881us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 379.202us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 379.202us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 14.000s 5705.328us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 415.645us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 56.000s 16986.057us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 415.645us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 415.645us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 379.202us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 415.645us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 9.000s 405.760us 1 1 100.00