Simulation Results: sysrst_ctrl

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.94 %
  • code
  • 93.71 %
  • assert
  • 94.35 %
  • func
  • 57.75 %
  • line
  • 97.71 %
  • branch
  • 97.48 %
  • cond
  • 95.15 %
  • toggle
  • 100.00 %
  • FSM
  • 78.21 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.290s 2113.339us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 3.280s 2482.476us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.860s 2434.578us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.260s 2554.001us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 13.290s 6028.462us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 2.910s 2039.697us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 17.420s 39330.373us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 7.270s 2720.245us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 5.010s 2041.374us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 2.910s 2039.697us 1 1 100.00
sysrst_ctrl_csr_aliasing 7.270s 2720.245us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 235.750s 131137.276us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 20.540s 24342.394us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 99.650s 189015.510us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 4.400s 3745.833us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.980s 2524.028us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 2.840s 2194.033us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 2.790s 4745.094us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 3.170s 2619.453us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 2.650s 2631.560us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 5.280s 34870.799us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 2.610s 9574.928us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.600s 2038.947us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 1.150s 2063.883us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 6.650s 2040.524us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 6.650s 2040.524us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 13.290s 6028.462us 1 1 100.00
sysrst_ctrl_csr_rw 2.910s 2039.697us 1 1 100.00
sysrst_ctrl_csr_aliasing 7.270s 2720.245us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 5.030s 4970.675us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 13.290s 6028.462us 1 1 100.00
sysrst_ctrl_csr_rw 2.910s 2039.697us 1 1 100.00
sysrst_ctrl_csr_aliasing 7.270s 2720.245us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 5.030s 4970.675us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 40.370s 22014.469us 1 1 100.00
sysrst_ctrl_tl_intg_err 45.890s 22242.538us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 45.890s 22242.538us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 9.100s 9499.444us 1 1 100.00