Simulation Results: uart

 
22/04/2026 15:30:23 DVSim: v1.32.0 sha: 69602b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.71 %
  • code
  • 96.68 %
  • assert
  • 97.12 %
  • func
  • 54.33 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 97.55 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.170s 282.489us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.620s 16.299us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.640s 19.326us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.520s 349.737us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.720s 102.341us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.670s 15.127us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.640s 19.326us 1 1 100.00
uart_csr_aliasing 0.720s 102.341us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 101.980s 103366.752us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.170s 282.489us 1 1 100.00
uart_tx_rx 101.980s 103366.752us 1 1 100.00
parity_error 2 2 100.00
uart_intr 105.150s 300797.603us 1 1 100.00
uart_rx_parity_err 10.240s 26250.101us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 101.980s 103366.752us 1 1 100.00
uart_intr 105.150s 300797.603us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 198.960s 112536.040us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 209.930s 137904.416us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 27.040s 83842.290us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 105.150s 300797.603us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 105.150s 300797.603us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 105.150s 300797.603us 1 1 100.00
perf 1 1 100.00
uart_perf 220.000s 14935.053us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 10.030s 1726.385us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 10.030s 1726.385us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 11.840s 56765.306us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 22.170s 37268.202us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.880s 3646.715us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 29.520s 4384.977us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 129.970s 29545.648us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 189.970s 241589.709us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.750s 22.193us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.680s 14.868us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.710s 174.487us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.710s 174.487us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.620s 16.299us 1 1 100.00
uart_csr_rw 0.640s 19.326us 1 1 100.00
uart_csr_aliasing 0.720s 102.341us 1 1 100.00
uart_same_csr_outstanding 0.940s 15.770us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.620s 16.299us 1 1 100.00
uart_csr_rw 0.640s 19.326us 1 1 100.00
uart_csr_aliasing 0.720s 102.341us 1 1 100.00
uart_same_csr_outstanding 0.940s 15.770us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.060s 63.224us 1 1 100.00
uart_tl_intg_err 1.000s 149.362us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.000s 149.362us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 14.690s 6493.919us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *
uart_noise_filter 90841515220368404886978856413901665534016272439148721715976197600518230825207 78
UVM_ERROR @ 50799609248 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 50799942583 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (48 [0x30] vs 251 [0xfb]) reg name: uart_reg_block.rdata
UVM_ERROR @ 50800009250 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 50800142584 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (48 [0x30] vs 255 [0xff]) reg name: uart_reg_block.rdata