Simulation Results: adc_ctrl

 
23/04/2026 15:30:30 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.24 %
  • code
  • 93.12 %
  • assert
  • 90.92 %
  • func
  • 11.69 %
  • line
  • 97.97 %
  • branch
  • 96.35 %
  • cond
  • 85.28 %
  • toggle
  • 99.53 %
  • FSM
  • 86.49 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 11.750s 5813.883us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.430s 665.834us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.340s 470.651us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 21.650s 11207.035us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.720s 861.097us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.060s 465.541us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.340s 470.651us 1 1 100.00
adc_ctrl_csr_aliasing 2.720s 861.097us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 1.120s 447.122us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 1.290s 383.774us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.750s 486.781us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 1.260s 403.276us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.820s 447.102us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 1.140s 309.690us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 0.710s 307.874us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 1.270s 335.826us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 8.170s 4359.135us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 13.320s 30242.756us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 159.610s 94320.681us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 1.860s 798.942us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.950s 399.989us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.860s 317.264us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.370s 341.479us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.370s 341.479us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.430s 665.834us 1 1 100.00
adc_ctrl_csr_rw 1.340s 470.651us 1 1 100.00
adc_ctrl_csr_aliasing 2.720s 861.097us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.530s 2136.343us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.430s 665.834us 1 1 100.00
adc_ctrl_csr_rw 1.340s 470.651us 1 1 100.00
adc_ctrl_csr_aliasing 2.720s 861.097us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.530s 2136.343us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 2.070s 4420.112us 1 1 100.00
adc_ctrl_tl_intg_err 10.090s 4117.116us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 10.090s 4117.116us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 1.050s 777.285us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *]
adc_ctrl_filters_polled 21534903482579241631008084611837431275771008289898616506267862831163702388469 389
UVM_INFO @ 447121922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 33110733716599877708068537999062549980490835915234670332424167701559492174176 389
UVM_INFO @ 383774143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 33224589147525432658018100761470584388260646970051283105473030360154240179931 389
UVM_INFO @ 486780547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 10982991013250497382128967159660202312517835939978087748042387173118335957135 389
UVM_INFO @ 403275522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 447584207358478257223087519761707323492489429986705252733030093957442074644 389
UVM_INFO @ 447101885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 81232250653768992448755152131993226489688202430137363705318979394931081595314 389
UVM_INFO @ 309689507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 23939789525596971188356248994494595689780150281883997248499708270264026488712 389
UVM_INFO @ 335826041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 97427800868152035204484597039236744447681244133122322450247632069167003040411 389
UVM_INFO @ 307874279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 96883724673995577829663699945115895364415728700930767369171828165221773732488 395
UVM_INFO @ 777284557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 40668334619678300859075024569910274312303001984678562708197035326396301147723 390
UVM_INFO @ 798942327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---