Simulation Results: aes/masked

 
23/04/2026 15:30:30 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.58 %
  • code
  • 95.25 %
  • assert
  • 98.29 %
  • func
  • 66.21 %
  • block
  • 95.91 %
  • line
  • 97.61 %
  • branch
  • 89.84 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
89.47%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 115.746us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 104.777us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 77.134us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 86.025us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 191.774us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 229.971us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 72.471us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 86.025us 1 1 100.00
aes_csr_aliasing 2.000s 229.971us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 104.777us 1 1 100.00
aes_config_error 6.000s 448.673us 1 1 100.00
aes_stress 2.000s 60.653us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 104.777us 1 1 100.00
aes_config_error 6.000s 448.673us 1 1 100.00
aes_stress 2.000s 60.653us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 60.653us 1 1 100.00
aes_b2b 22.000s 417.611us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 60.653us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 3.000s 104.777us 1 1 100.00
aes_config_error 6.000s 448.673us 1 1 100.00
aes_stress 2.000s 60.653us 1 1 100.00
aes_alert_reset 53.000s 10019.914us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 111.865us 1 1 100.00
aes_config_error 6.000s 448.673us 1 1 100.00
aes_alert_reset 53.000s 10019.914us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 186.126us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 2337.563us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 8.000s 614.934us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 53.000s 10019.914us 0 1 0.00
stress 1 1 100.00
aes_stress 2.000s 60.653us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 60.653us 1 1 100.00
aes_sideload 4.000s 171.248us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 4.000s 97.141us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 63.000s 10007.536us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 81.910us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 102.897us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 483.400us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 483.400us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 77.134us 1 1 100.00
aes_csr_rw 2.000s 86.025us 1 1 100.00
aes_csr_aliasing 2.000s 229.971us 1 1 100.00
aes_same_csr_outstanding 2.000s 97.529us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 77.134us 1 1 100.00
aes_csr_rw 2.000s 86.025us 1 1 100.00
aes_csr_aliasing 2.000s 229.971us 1 1 100.00
aes_same_csr_outstanding 2.000s 97.529us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 696.533us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 26.000s 10041.144us 0 1 0.00
aes_control_fi 3.000s 60.556us 1 1 100.00
aes_cipher_fi 3.000s 96.737us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 128.908us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 128.908us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 128.908us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 128.908us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 288.511us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 6.000s 1147.262us 1 1 100.00
aes_tl_intg_err 2.000s 308.245us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 308.245us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 53.000s 10019.914us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 128.908us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 128.908us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 3.000s 104.777us 1 1 100.00
aes_stress 2.000s 60.653us 1 1 100.00
aes_alert_reset 53.000s 10019.914us 0 1 0.00
aes_core_fi 2.000s 109.379us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 81.910us 1 1 100.00
aes_config_error 6.000s 448.673us 1 1 100.00
aes_stress 2.000s 60.653us 1 1 100.00
aes_core_fi 2.000s 109.379us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 128.908us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 136.384us 1 1 100.00
aes_stress 2.000s 60.653us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 60.653us 1 1 100.00
aes_sideload 4.000s 171.248us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 136.384us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 136.384us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 136.384us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 136.384us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 136.384us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 60.653us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 60.653us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 26.000s 10041.144us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 26.000s 10041.144us 0 1 0.00
aes_control_fi 3.000s 60.556us 1 1 100.00
aes_cipher_fi 3.000s 96.737us 1 1 100.00
aes_ctr_fi 3.000s 59.801us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 26.000s 10041.144us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 26.000s 10041.144us 0 1 0.00
aes_control_fi 3.000s 60.556us 1 1 100.00
aes_cipher_fi 3.000s 96.737us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 96.737us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 26.000s 10041.144us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 26.000s 10041.144us 0 1 0.00
aes_control_fi 3.000s 60.556us 1 1 100.00
aes_ctr_fi 3.000s 59.801us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 26.000s 10041.144us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 26.000s 10041.144us 0 1 0.00
aes_control_fi 3.000s 60.556us 1 1 100.00
aes_cipher_fi 3.000s 96.737us 1 1 100.00
aes_ctr_fi 3.000s 59.801us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 53.000s 10019.914us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 26.000s 10041.144us 0 1 0.00
aes_control_fi 3.000s 60.556us 1 1 100.00
aes_cipher_fi 3.000s 96.737us 1 1 100.00
aes_ctr_fi 3.000s 59.801us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 26.000s 10041.144us 0 1 0.00
aes_control_fi 3.000s 60.556us 1 1 100.00
aes_cipher_fi 3.000s 96.737us 1 1 100.00
aes_ctr_fi 3.000s 59.801us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 26.000s 10041.144us 0 1 0.00
aes_control_fi 3.000s 60.556us 1 1 100.00
aes_ctr_fi 3.000s 59.801us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 26.000s 10041.144us 0 1 0.00
aes_ghash_fi 3.000s 186.624us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 26.000s 10041.144us 0 1 0.00
aes_control_fi 3.000s 60.556us 1 1 100.00
aes_cipher_fi 3.000s 96.737us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 21.000s 1840.143us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 60142768591205556115858923506164293884481172730879037520539576139129178644791 880
UVM_INFO @ 10019913821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 34873392944085723174265553203863406340888626895585520663322024229465495608059 1400
UVM_INFO @ 10007535834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 37374986175385696316350125937640864766691694087508012497582633547094784100354 5495
UVM_INFO @ 10041144347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 98675547320936304647804839758577737175086932625522981636205220471544443959724 302
UVM_INFO @ 1840143213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---