Simulation Results: aes/unmasked

 
23/04/2026 15:30:30 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.33 %
  • code
  • 91.41 %
  • assert
  • 97.75 %
  • func
  • 66.82 %
  • block
  • 91.47 %
  • line
  • 93.91 %
  • branch
  • 84.40 %
  • toggle
  • 97.99 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
89.47%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 76.020us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 119.837us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 87.145us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 54.926us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 185.338us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 351.236us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 63.989us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 54.926us 1 1 100.00
aes_csr_aliasing 3.000s 351.236us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 119.837us 1 1 100.00
aes_config_error 2.000s 689.724us 1 1 100.00
aes_stress 3.000s 70.214us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 119.837us 1 1 100.00
aes_config_error 2.000s 689.724us 1 1 100.00
aes_stress 3.000s 70.214us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 70.214us 1 1 100.00
aes_b2b 4.000s 139.984us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 70.214us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 3.000s 119.837us 1 1 100.00
aes_config_error 2.000s 689.724us 1 1 100.00
aes_stress 3.000s 70.214us 1 1 100.00
aes_alert_reset 10.000s 10029.701us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 1.000s 73.592us 1 1 100.00
aes_config_error 2.000s 689.724us 1 1 100.00
aes_alert_reset 10.000s 10029.701us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 154.891us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 1007.095us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 4.000s 284.496us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 10.000s 10029.701us 0 1 0.00
stress 1 1 100.00
aes_stress 3.000s 70.214us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 70.214us 1 1 100.00
aes_sideload 3.000s 145.376us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 215.505us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 22.000s 10781.888us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 2.000s 59.859us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 83.620us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 120.533us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 120.533us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 87.145us 1 1 100.00
aes_csr_rw 1.000s 54.926us 1 1 100.00
aes_csr_aliasing 3.000s 351.236us 1 1 100.00
aes_same_csr_outstanding 2.000s 98.623us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 87.145us 1 1 100.00
aes_csr_rw 1.000s 54.926us 1 1 100.00
aes_csr_aliasing 3.000s 351.236us 1 1 100.00
aes_same_csr_outstanding 2.000s 98.623us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 220.020us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 26.000s 10013.491us 0 1 0.00
aes_control_fi 1.000s 45.224us 1 1 100.00
aes_cipher_fi 2.000s 67.519us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 3.000s 387.521us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 3.000s 387.521us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 3.000s 387.521us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 3.000s 387.521us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 341.287us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 6.000s 1550.613us 1 1 100.00
aes_tl_intg_err 2.000s 204.112us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 204.112us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 10.000s 10029.701us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 387.521us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 387.521us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 3.000s 119.837us 1 1 100.00
aes_stress 3.000s 70.214us 1 1 100.00
aes_alert_reset 10.000s 10029.701us 0 1 0.00
aes_core_fi 2.000s 95.021us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 2.000s 59.859us 1 1 100.00
aes_config_error 2.000s 689.724us 1 1 100.00
aes_stress 3.000s 70.214us 1 1 100.00
aes_core_fi 2.000s 95.021us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 387.521us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 114.383us 1 1 100.00
aes_stress 3.000s 70.214us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 70.214us 1 1 100.00
aes_sideload 3.000s 145.376us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 114.383us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 114.383us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 114.383us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 114.383us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 114.383us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 70.214us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 70.214us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 26.000s 10013.491us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 26.000s 10013.491us 0 1 0.00
aes_control_fi 1.000s 45.224us 1 1 100.00
aes_cipher_fi 2.000s 67.519us 1 1 100.00
aes_ctr_fi 2.000s 86.408us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 26.000s 10013.491us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 26.000s 10013.491us 0 1 0.00
aes_control_fi 1.000s 45.224us 1 1 100.00
aes_cipher_fi 2.000s 67.519us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 67.519us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 26.000s 10013.491us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 26.000s 10013.491us 0 1 0.00
aes_control_fi 1.000s 45.224us 1 1 100.00
aes_ctr_fi 2.000s 86.408us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 26.000s 10013.491us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 26.000s 10013.491us 0 1 0.00
aes_control_fi 1.000s 45.224us 1 1 100.00
aes_cipher_fi 2.000s 67.519us 1 1 100.00
aes_ctr_fi 2.000s 86.408us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 10.000s 10029.701us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 26.000s 10013.491us 0 1 0.00
aes_control_fi 1.000s 45.224us 1 1 100.00
aes_cipher_fi 2.000s 67.519us 1 1 100.00
aes_ctr_fi 2.000s 86.408us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 26.000s 10013.491us 0 1 0.00
aes_control_fi 1.000s 45.224us 1 1 100.00
aes_cipher_fi 2.000s 67.519us 1 1 100.00
aes_ctr_fi 2.000s 86.408us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 26.000s 10013.491us 0 1 0.00
aes_control_fi 1.000s 45.224us 1 1 100.00
aes_ctr_fi 2.000s 86.408us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 26.000s 10013.491us 0 1 0.00
aes_ghash_fi 1.000s 53.950us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 26.000s 10013.491us 0 1 0.00
aes_control_fi 1.000s 45.224us 1 1 100.00
aes_cipher_fi 2.000s 67.519us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 15.000s 3778.740us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 14951494374285006605750996448165406913962315695865939188217649661088594369184 354
UVM_INFO @ 10029700853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 22833331099900522314655846013559759119516313192167894291566375939299922024541 11892
UVM_INFO @ 10781888005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 103166645097454709564905424734613151429198552552537588088265167615818283482786 2574
UVM_INFO @ 10013490971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
aes_stress_all_with_rand_reset 89073166608696427920516787926818121990371676929043827414506635471431605680542 295
UVM_INFO @ 3778739916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---