Simulation Results: alert_handler

 
23/04/2026 15:30:30 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.09 %
  • code
  • 90.99 %
  • assert
  • 98.14 %
  • func
  • 81.14 %
  • line
  • 99.66 %
  • branch
  • 98.64 %
  • cond
  • 92.40 %
  • toggle
  • 90.07 %
  • FSM
  • 74.19 %
Validation stages
V1
100.00%
V2
94.74%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 38.190s 1133.708us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 7.020s 168.421us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 2.810s 68.685us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 69.540s 10209.472us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 102.650s 4415.086us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 3.370s 34.135us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 2.810s 68.685us 1 1 100.00
alert_handler_csr_aliasing 102.650s 4415.086us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 68.490s 4191.710us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 2.360s 16.193us 1 1 100.00
entropy 0 1 0.00
alert_handler_entropy 389.550s 45370.454us 0 1 0.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 5.480s 50.988us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 38.190s 1133.708us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 20.130s 3247.708us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 14.460s 770.538us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 95.580s 31018.190us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 1538.860s 85956.084us 1 1 100.00
alert_handler_lpg_stub_clk 1414.810s 68533.848us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1478.940s 40477.744us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 10.140s 1081.672us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.420s 85.420us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.100s 14.950us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 5.910s 52.561us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 5.910s 52.561us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 7.020s 168.421us 1 1 100.00
alert_handler_csr_rw 2.810s 68.685us 1 1 100.00
alert_handler_csr_aliasing 102.650s 4415.086us 1 1 100.00
alert_handler_same_csr_outstanding 13.280s 1467.784us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 7.020s 168.421us 1 1 100.00
alert_handler_csr_rw 2.810s 68.685us 1 1 100.00
alert_handler_csr_aliasing 102.650s 4415.086us 1 1 100.00
alert_handler_same_csr_outstanding 13.280s 1467.784us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 217.500s 10245.329us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 217.500s 10245.329us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 217.500s 10245.329us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 217.500s 10245.329us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 406.520s 21482.635us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 19.080s 1817.575us 1 1 100.00
alert_handler_tl_intg_err 28.320s 1322.158us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 28.320s 1322.158us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 217.500s 10245.329us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 38.190s 1133.708us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 38.190s 1133.708us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 38.190s 1133.708us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 38.190s 1133.708us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 5.480s 50.988us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1538.860s 85956.084us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 5.480s 50.988us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 0 1 0.00
alert_handler_entropy 389.550s 45370.454us 0 1 0.00
sec_cm_esc_tx_intersig_bkgn_chk 0 1 0.00
alert_handler_entropy 389.550s 45370.454us 0 1 0.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 19.080s 1817.575us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 19.080s 1817.575us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 19.080s 1817.575us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 19.080s 1817.575us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 19.080s 1817.575us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 19.080s 1817.575us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 19.080s 1817.575us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 19.080s 1817.575us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 19.080s 1817.575us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 40.390s 2070.552us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalAlertPingFail)
alert_handler_entropy 42890276545232729472802065567237115495053160170343517890861017362718999846129 81
UVM_INFO @ 45370454205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
alert_handler_stress_all_with_rand_reset 63813993806269861037844349729419579497565325702772514534759592635690092845346 106
UVM_INFO @ 2070552200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---