| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| aon_timer_smoke | 1.150s | 664.851us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| aon_timer_csr_hw_reset | 2.510s | 1159.733us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| aon_timer_csr_rw | 0.930s | 536.827us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| aon_timer_csr_bit_bash | 7.510s | 14166.478us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| aon_timer_csr_aliasing | 1.380s | 487.222us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| aon_timer_csr_mem_rw_with_rand_reset | 1.030s | 520.677us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| aon_timer_csr_rw | 0.930s | 536.827us | 1 | 1 | 100.00 | |
| aon_timer_csr_aliasing | 1.380s | 487.222us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| aon_timer_mem_walk | 0.900s | 295.707us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| aon_timer_mem_partial_access | 0.840s | 320.756us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| prescaler | 1 | 1 | 100.00 | |||
| aon_timer_prescaler | 18.510s | 62055.246us | 1 | 1 | 100.00 | |
| jump | 1 | 1 | 100.00 | |||
| aon_timer_jump | 1.650s | 559.575us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| aon_timer_stress_all | 137.520s | 105299.064us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| aon_timer_alert_test | 0.900s | 431.392us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| aon_timer_intr_test | 0.750s | 376.635us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| aon_timer_tl_errors | 1.820s | 724.033us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| aon_timer_tl_errors | 1.820s | 724.033us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| aon_timer_csr_hw_reset | 2.510s | 1159.733us | 1 | 1 | 100.00 | |
| aon_timer_csr_rw | 0.930s | 536.827us | 1 | 1 | 100.00 | |
| aon_timer_csr_aliasing | 1.380s | 487.222us | 1 | 1 | 100.00 | |
| aon_timer_same_csr_outstanding | 1.860s | 1084.115us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| aon_timer_csr_hw_reset | 2.510s | 1159.733us | 1 | 1 | 100.00 | |
| aon_timer_csr_rw | 0.930s | 536.827us | 1 | 1 | 100.00 | |
| aon_timer_csr_aliasing | 1.380s | 487.222us | 1 | 1 | 100.00 | |
| aon_timer_same_csr_outstanding | 1.860s | 1084.115us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| aon_timer_sec_cm | 4.730s | 8086.536us | 1 | 1 | 100.00 | |
| aon_timer_tl_intg_err | 3.600s | 4021.120us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| aon_timer_tl_intg_err | 3.600s | 4021.120us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_threshold | 1 | 1 | 100.00 | |||
| aon_timer_smoke_max_thold | 1.040s | 510.390us | 1 | 1 | 100.00 | |
| min_threshold | 1 | 1 | 100.00 | |||
| aon_timer_smoke_min_thold | 1.450s | 721.305us | 1 | 1 | 100.00 | |
| wkup_count_hi_cdc | 1 | 1 | 100.00 | |||
| aon_timer_wkup_count_cdc_hi | 2.380s | 3974.802us | 1 | 1 | 100.00 | |
| custom_intr | 1 | 1 | 100.00 | |||
| aon_timer_custom_intr | 0.770s | 661.210us | 1 | 1 | 100.00 | |
| alternating_on_off | 1 | 1 | 100.00 | |||
| aon_timer_alternating_enable_on_off | 3.910s | 4263.234us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| aon_timer_stress_all_with_rand_reset | 6.370s | 4434.599us | 1 | 1 | 100.00 | |