Simulation Results: chip

 
23/04/2026 15:30:30 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.82 %
  • code
  • 84.51 %
  • assert
  • 97.37 %
  • func
  • 39.59 %
  • line
  • 94.03 %
  • branch
  • 92.35 %
  • cond
  • 87.83 %
  • toggle
  • 91.22 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
76.98%
V2S
50.00%
V3
61.54%
unmapped
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 161.750s 2770.825us 1 1 100.00
chip_sw_example_rom 78.860s 2751.162us 1 1 100.00
chip_sw_example_manufacturer 133.820s 2372.822us 1 1 100.00
chip_sw_example_concurrency 149.200s 3398.049us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 277.120s 6631.070us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 497.490s 5365.239us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 401.980s 6029.573us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 4077.500s 35869.259us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 66.090s 2319.401us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 4077.500s 35869.259us 1 1 100.00
chip_csr_rw 497.490s 5365.239us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 4.640s 47.403us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 293.200s 4740.527us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 293.200s 4740.527us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 293.200s 4740.527us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 334.570s 4213.366us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 334.570s 4213.366us 1 1 100.00
chip_sw_uart_tx_rx_idx1 392.070s 4756.298us 1 1 100.00
chip_sw_uart_tx_rx_idx2 345.130s 3643.031us 1 1 100.00
chip_sw_uart_tx_rx_idx3 387.460s 4338.647us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 1002.640s 8023.944us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1130.150s 8872.200us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 1012.870s 13065.567us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 224.620s 5742.921us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 224.620s 5742.921us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 0 1 0.00
chip_sw_sleep_pin_mio_dio_val 164.840s 2880.637us 0 1 0.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 288.320s 6558.640us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 153.280s 3093.408us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 96.320s 2788.728us 1 1 100.00
chip_tap_straps_testunlock0 128.720s 3418.502us 1 1 100.00
chip_tap_straps_rma 123.000s 2721.349us 1 1 100.00
chip_tap_straps_prod 1035.410s 16673.688us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 166.050s 2669.880us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 722.240s 8811.694us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 469.230s 5050.460us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 469.230s 5050.460us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 644.580s 8721.572us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1291.610s 12397.993us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 372.270s 4051.981us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 559.200s 5398.955us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3671.850s 18568.328us 1 1 100.00
chip_sw_aes_enc_jitter_en 147.040s 2399.660us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 594.210s 6456.803us 1 1 100.00
chip_sw_hmac_enc_jitter_en 198.730s 3365.831us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1582.410s 12048.467us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 186.980s 2775.315us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 368.420s 4894.954us 1 1 100.00
chip_sw_clkmgr_jitter 140.110s 2666.975us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 191.810s 3109.759us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 676.270s 9066.250us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 293.950s 5628.084us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 128.270s 3037.787us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 293.950s 5628.084us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 141.550s 2978.387us 1 1 100.00
chip_sw_aes_smoketest 181.360s 3201.783us 1 1 100.00
chip_sw_aon_timer_smoketest 172.360s 3076.421us 1 1 100.00
chip_sw_clkmgr_smoketest 152.490s 2740.931us 1 1 100.00
chip_sw_csrng_smoketest 181.000s 3395.639us 1 1 100.00
chip_sw_entropy_src_smoketest 885.680s 6498.401us 1 1 100.00
chip_sw_gpio_smoketest 207.060s 3689.894us 1 1 100.00
chip_sw_hmac_smoketest 239.570s 3403.117us 1 1 100.00
chip_sw_kmac_smoketest 177.660s 3059.978us 1 1 100.00
chip_sw_otbn_smoketest 1325.670s 10098.979us 1 1 100.00
chip_sw_pwrmgr_smoketest 253.120s 6044.519us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 257.700s 6225.732us 1 1 100.00
chip_sw_rv_plic_smoketest 160.700s 3198.650us 1 1 100.00
chip_sw_rv_timer_smoketest 171.150s 2744.054us 1 1 100.00
chip_sw_rstmgr_smoketest 139.210s 3087.033us 1 1 100.00
chip_sw_sram_ctrl_smoketest 150.340s 2565.032us 1 1 100.00
chip_sw_uart_smoketest 153.420s 2990.349us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 123.260s 3119.196us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 332.250s 4782.871us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 8022.140s 63516.137us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3077.560s 14302.776us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 113.899s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 189.640s 3434.477us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 195.100s 3591.273us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7143.350s 54519.225us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7724.330s 59919.655us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 64.440s 2613.848us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 64.440s 2613.848us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 4077.500s 35869.259us 1 1 100.00
chip_same_csr_outstanding 3053.830s 29900.783us 1 1 100.00
chip_csr_hw_reset 277.120s 6631.070us 1 1 100.00
chip_csr_rw 497.490s 5365.239us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 4077.500s 35869.259us 1 1 100.00
chip_same_csr_outstanding 3053.830s 29900.783us 1 1 100.00
chip_csr_hw_reset 277.120s 6631.070us 1 1 100.00
chip_csr_rw 497.490s 5365.239us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 45.040s 2060.673us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 5.400s 51.319us 1 1 100.00
xbar_smoke_large_delays 58.090s 9742.439us 1 1 100.00
xbar_smoke_slow_rsp 55.650s 6193.279us 1 1 100.00
xbar_random_zero_delays 12.370s 168.769us 1 1 100.00
xbar_random_large_delays 61.750s 10054.309us 1 1 100.00
xbar_random_slow_rsp 124.920s 13740.893us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 13.900s 145.885us 1 1 100.00
xbar_error_and_unmapped_addr 16.280s 698.467us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 10.010s 162.549us 1 1 100.00
xbar_error_and_unmapped_addr 16.280s 698.467us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 45.060s 1825.123us 1 1 100.00
xbar_access_same_device_slow_rsp 332.340s 36639.544us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 36.720s 2004.147us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 25.850s 1162.192us 1 1 100.00
xbar_stress_all_with_error 65.790s 1640.915us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 115.170s 381.100us 1 1 100.00
xbar_stress_all_with_reset_error 35.780s 173.095us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3077.560s 14302.776us 1 1 100.00
rom_e2e_shutdown_output 0 1 0.00
rom_e2e_shutdown_output 2094.440s 31790.315us 0 1 0.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2900.280s 15869.258us 1 1 100.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 125.820s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 9.574s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 12.573s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 13.665s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 14.654s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 153.028s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 11.188s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 14.537s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 9.990s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 12.097s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 58.435s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 75.479s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 118.413s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 104.827s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 88.831s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 16.240s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 17.160s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 17.510s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 17.610s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 21.010s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 16.790s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 20.580s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 20.730s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 17.490s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 16.320s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 17.140s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 16.630s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 16.670s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 17.190s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 16.790s 10.380us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 165.368s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 14.426s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 76.985s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 10.813s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 66.169s 0.000us 0 1 0.00
rom_e2e_keymgr_init 2 3 66.67
rom_e2e_keymgr_init_rom_ext_meas 5872.830s 29182.028us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 3167.400s 16268.898us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 5783.460s 29662.498us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3286.640s 16187.707us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3294.980s 34491.877us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3294.980s 34491.877us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 195.270s 3476.702us 1 1 100.00
chip_sw_aes_enc_jitter_en 147.040s 2399.660us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 138.690s 3171.373us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 161.800s 3116.210us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1718.940s 13839.182us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 197.110s 2734.797us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 264.770s 4565.768us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 400.550s 5685.608us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 524.930s 5068.260us 1 1 100.00
chip_plic_all_irqs_10 323.480s 4403.167us 1 1 100.00
chip_plic_all_irqs_20 416.260s 3940.076us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 209.290s 3254.130us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1151.120s 11544.124us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 276.250s 5169.234us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 133.990s 2902.733us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 704.620s 6701.469us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1144.230s 8451.651us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 847.380s 8236.525us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 7688.470s 254762.042us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 257.890s 3956.377us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 253.120s 6044.519us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 257.890s 3956.377us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 533.360s 7714.429us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 533.360s 7714.429us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 277.870s 7682.326us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 375.860s 6035.392us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 628.650s 6207.903us 1 1 100.00
chip_sw_aes_idle 161.800s 3116.210us 1 1 100.00
chip_sw_hmac_enc_idle 184.240s 2747.899us 1 1 100.00
chip_sw_kmac_idle 148.060s 2730.379us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 316.050s 4711.840us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 336.670s 4179.196us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 275.270s 4954.047us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 335.130s 4056.241us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 991.180s 12932.160us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 390.100s 4327.179us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 365.480s 5285.159us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 382.770s 4162.730us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 365.020s 5273.197us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 424.610s 4378.439us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 419.640s 5485.948us 1 1 100.00
chip_sw_ast_clk_outputs 644.580s 8721.572us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 488.990s 10290.244us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 382.770s 4162.730us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 365.020s 5273.197us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 372.270s 4051.981us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 559.200s 5398.955us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3671.850s 18568.328us 1 1 100.00
chip_sw_aes_enc_jitter_en 147.040s 2399.660us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 594.210s 6456.803us 1 1 100.00
chip_sw_hmac_enc_jitter_en 198.730s 3365.831us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1582.410s 12048.467us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 186.980s 2775.315us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 368.420s 4894.954us 1 1 100.00
chip_sw_clkmgr_jitter 140.110s 2666.975us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 151.450s 3128.761us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 406.170s 5057.759us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 617.050s 7337.388us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3816.850s 25013.969us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 181.000s 2895.809us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 162.240s 3167.348us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 666.460s 8589.496us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 208.650s 3710.969us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 367.970s 5628.583us 1 1 100.00
chip_sw_flash_init_reduced_freq 1155.110s 19782.453us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 3272.110s 25671.498us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 644.580s 8721.572us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 380.550s 4544.989us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 244.420s 3497.804us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 400.550s 5685.608us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 704.620s 6701.469us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2307.180s 24170.683us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 171.150s 3161.175us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 475.170s 6750.730us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 184.720s 3253.399us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 3563.480s 21358.417us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 137.460s 2541.477us 1 1 100.00
chip_sw_edn_entropy_reqs 848.860s 7689.494us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 137.460s 2541.477us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2307.180s 24170.683us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 132.460s 2282.347us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1145.170s 17747.621us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 571.960s 5464.204us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 559.200s 5398.955us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 351.400s 4342.008us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 372.270s 4051.981us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3169.450s 42367.491us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1145.170s 17747.621us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 177.990s 3548.887us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1174.710s 9593.934us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 138.330s 3232.875us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3169.450s 42367.491us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 138.330s 3232.875us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 138.330s 3232.875us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 138.330s 3232.875us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 138.330s 3232.875us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 400.550s 5685.608us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 103.880s 4919.312us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 561.760s 5669.025us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 409.450s 4520.208us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 409.450s 4520.208us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 170.760s 2670.943us 1 1 100.00
chip_sw_hmac_enc_jitter_en 198.730s 3365.831us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 184.240s 2747.899us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 933.520s 7382.494us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 705.610s 6240.767us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 468.050s 5290.086us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 456.790s 5705.820us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 415.630s 5118.809us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 277.010s 3799.729us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1174.710s 9593.934us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1582.410s 12048.467us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1466.800s 12018.609us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1718.940s 13839.182us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2582.310s 13728.871us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 124.800s 2816.229us 1 1 100.00
chip_sw_kmac_mode_kmac 190.680s 2668.848us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 186.980s 2775.315us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1174.710s 9593.934us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 525.940s 9587.842us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 141.150s 2988.996us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 948.960s 7984.335us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 148.060s 2730.379us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 264.770s 4565.768us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 96.320s 2788.728us 1 1 100.00
chip_tap_straps_rma 123.000s 2721.349us 1 1 100.00
chip_tap_straps_prod 1035.410s 16673.688us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 168.350s 3714.508us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 525.940s 9587.842us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 525.940s 9587.842us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 525.940s 9587.842us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1476.970s 11580.545us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 138.330s 3232.875us 0 1 0.00
chip_sw_flash_rma_unlocked 3169.450s 42367.491us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 210.370s 3154.170us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 558.440s 7708.852us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 523.030s 7176.718us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 469.370s 5748.089us 0 1 0.00
chip_sw_lc_ctrl_transition 525.940s 9587.842us 1 1 100.00
chip_sw_keymgr_key_derivation 1174.710s 9593.934us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 372.940s 8813.631us 1 1 100.00
chip_sw_sram_ctrl_execution_main 655.590s 9100.541us 1 1 100.00
chip_prim_tl_access 103.880s 4919.312us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 488.990s 10290.244us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 390.100s 4327.179us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 365.480s 5285.159us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 382.770s 4162.730us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 365.020s 5273.197us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 424.610s 4378.439us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 419.640s 5485.948us 1 1 100.00
chip_tap_straps_dev 96.320s 2788.728us 1 1 100.00
chip_tap_straps_rma 123.000s 2721.349us 1 1 100.00
chip_tap_straps_prod 1035.410s 16673.688us 1 1 100.00
chip_rv_dm_lc_disabled 170.410s 5638.329us 0 1 0.00
chip_lc_scrap 3 4 75.00
chip_sw_lc_ctrl_rma_to_scrap 182.200s 3642.439us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 96.480s 3650.040us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 98.450s 3536.094us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 1860.790s 26759.670us 0 1 0.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 1589.640s 31913.506us 1 1 100.00
chip_rv_dm_lc_disabled 170.410s 5638.329us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 637.770s 9882.389us 0 1 0.00
chip_sw_lc_walkthrough_prod 679.720s 11808.209us 0 1 0.00
chip_sw_lc_walkthrough_prodend 619.080s 10676.674us 1 1 100.00
chip_sw_lc_walkthrough_rma 367.950s 6772.429us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1589.640s 31913.506us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 56.350s 2598.729us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 69.860s 2595.970us 1 1 100.00
rom_volatile_raw_unlock 35.451s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3603.300s 17213.661us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3671.850s 18568.328us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 628.650s 6207.903us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 628.650s 6207.903us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 628.650s 6207.903us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 292.860s 3409.031us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 525.940s 9587.842us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1145.170s 17747.621us 1 1 100.00
chip_sw_otbn_mem_scramble 292.860s 3409.031us 1 1 100.00
chip_sw_keymgr_key_derivation 1174.710s 9593.934us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 368.330s 5555.547us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 197.970s 3410.434us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1145.170s 17747.621us 1 1 100.00
chip_sw_otbn_mem_scramble 292.860s 3409.031us 1 1 100.00
chip_sw_keymgr_key_derivation 1174.710s 9593.934us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 368.330s 5555.547us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 197.970s 3410.434us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 525.940s 9587.842us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 313.040s 4593.544us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 168.350s 3714.508us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 210.370s 3154.170us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 558.440s 7708.852us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 523.030s 7176.718us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 469.370s 5748.089us 0 1 0.00
chip_sw_lc_ctrl_transition 525.940s 9587.842us 1 1 100.00
chip_prim_tl_access 103.880s 4919.312us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 103.880s 4919.312us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 793.680s 7190.488us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 75.500s 2471.748us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 853.420s 22457.899us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 179.360s 6997.047us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 381.000s 8044.873us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 410.050s 6858.041us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 915.080s 24228.736us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1 2 50.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 482.960s 9795.311us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 533.360s 7714.429us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 908.370s 10708.741us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 355.790s 5614.003us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 75.500s 2471.748us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 328.520s 5476.895us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1449.060s 23692.376us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 261.000s 7546.572us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 151.550s 2808.090us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1433.850s 20659.435us 1 1 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 627.000s 8014.720us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 991.500s 10266.999us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1289.500s 23436.396us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 170.580s 3568.781us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 400.550s 5685.608us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 372.940s 8813.631us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 372.940s 8813.631us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 4 4 100.00
chip_sw_pwrmgr_all_reset_reqs 991.500s 10266.999us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1433.850s 20659.435us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 355.790s 5614.003us 1 1 100.00
chip_sw_pwrmgr_smoketest 253.120s 6044.519us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 286.370s 5456.930us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 518.560s 6841.526us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 248.020s 3763.661us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1151.120s 11544.124us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 165.060s 3495.524us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 400.550s 5685.608us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1144.230s 8451.651us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 495.840s 4506.794us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 455.220s 4780.289us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 154.610s 3186.904us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 197.970s 3410.434us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 518.560s 6841.526us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 518.560s 6841.526us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 660.760s 10245.233us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 987.080s 13995.767us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 286.370s 5456.930us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 145.090s 2995.128us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 309.340s 5209.643us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 123.000s 2721.349us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 170.410s 5638.329us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 524.930s 5068.260us 1 1 100.00
chip_plic_all_irqs_10 323.480s 4403.167us 1 1 100.00
chip_plic_all_irqs_20 416.260s 3940.076us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 125.210s 2933.626us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 213.060s 3241.368us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3077.560s 14302.776us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 593.350s 8801.416us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 243.100s 3861.134us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 221.370s 3593.004us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 175.360s 2975.978us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 368.330s 5555.547us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 368.420s 4894.954us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 465.080s 8221.643us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 359.750s 8826.123us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 655.590s 9100.541us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 400.550s 5685.608us 1 1 100.00
chip_sw_data_integrity_escalation 469.230s 5050.460us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 627.000s 8014.720us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1035.210s 23675.978us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 139.140s 2503.772us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 202.090s 4012.627us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 290.610s 4668.820us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1035.210s 23675.978us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1035.210s 23675.978us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2396.460s 20875.858us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2396.460s 20875.858us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 276.890s 5372.891us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3294.980s 34491.877us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 135.930s 3096.512us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 151.580s 3168.790us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 289.020s 4155.960us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 308.000s 3613.542us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1025.520s 8693.740us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5500.780s 31967.509us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1881.270s 12091.966us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 178.320s 2634.641us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 171.680s 2845.665us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 0 1 0.00
chip_sw_rv_core_ibex_lockstep_glitch 154.910s 2786.243us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9855.250s 71334.403us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1089.710s 6883.137us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 381.220s 6008.743us 0 1 0.00
rom_e2e_jtag_debug_dev 409.870s 5975.400us 0 1 0.00
rom_e2e_jtag_debug_rma 395.230s 6807.131us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 62.440s 1878.606us 0 1 0.00
rom_e2e_jtag_inject_dev 90.930s 3319.358us 0 1 0.00
rom_e2e_jtag_inject_rma 74.970s 2490.245us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 112.280s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 322.810s 3823.341us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 333.520s 3003.821us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 476.900s 3801.218us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 626.290s 6109.046us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 243.280s 2798.387us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 614.910s 5506.322us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 71.570s 2142.113us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 160.720s 2830.279us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 0 1 0.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 311.390s 6200.383us 0 1 0.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 267.180s 4436.036us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 991.500s 10266.999us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 381.220s 6008.743us 0 1 0.00
rom_e2e_jtag_debug_dev 409.870s 5975.400us 0 1 0.00
rom_e2e_jtag_debug_rma 395.230s 6807.131us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 344.830s 5379.705us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 400.550s 5685.608us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5400.400s 38812.591us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5400.400s 38812.591us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 155.560s 3671.339us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 334.570s 4213.366us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3118.340s 18750.563us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 8 10 80.00
chip_sival_flash_info_access 192.430s 2595.898us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 440.160s 5652.111us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 4.860s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 141.260s 2706.063us 1 1 100.00
chip_sw_otp_ctrl_descrambling 218.380s 3079.283us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 239.820s 3819.868us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 7.742s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 160.780s 3183.639us 1 1 100.00
ate_bootstrap_flash_erase 6463.700s 45235.513us 1 1 100.00
ate_bootstrap_disjoint 9711.300s 84891.640us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*]
chip_sw_sleep_pin_mio_dio_val 48980596835458529134313224255995137824347221917207896215383565844438341007189 451
UVM_INFO @ 2880.636500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch
chip_sw_spi_device_pass_through_collision 32271212009386521514538605873050042113137576255440309385100303693254338891238 322
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_flash_ctrl_lc_rw_en 80682056589739893768409493257108663659580556622683293346752977003603869683993 309
UVM_INFO @ 3232.875176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 92807962686821961974660056818780937089431760885979746383332114542471468544702 342
UVM_INFO @ 5748.088720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 87885140720996675932723721612510189177841450888275100016180868285591903638751 316
UVM_ERROR @ 2830.279366 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2830.279366 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 65590327209662365232646533804741123880628782943551815701012477282638712865801 312
UVM_ERROR @ 3161.174766 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3161.174766 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
chip_sw_otp_ctrl_rot_auth_config 14021447407621549951130221417395696361374427434835871441897728635308195604886 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:845) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched!
chip_sw_lc_ctrl_rand_to_scrap 44985480930687793800526958932358144178470447187597811288703417303289926736907 313
UVM_INFO @ 26759.669801 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_lc_walkthrough_dev 25372706745041461898488217777184170370204193032073916150495388749766574980380 369
UVM_INFO @ 9882.388862 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 68367887132228888355897428621567315832170385118563398294172789287017398991116 369
UVM_INFO @ 11808.209400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 29525522858637591436306069417166262778006142037108078740751720308052129895283 341
UVM_INFO @ 6772.428620 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'
chip_sw_pwrmgr_full_aon_reset 61160284666665332101628408460874257634628772419366071237459540997833053344019 303
UVM_ERROR @ 2471.747750 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 2471.747750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 35763398907017928503981571985107210294749982199198274135822111505680520197572 327
UVM_ERROR @ 9795.311000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9795.311000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 54892085682451640079309801074365983375367712627626266379377804884668111314586 325
UVM_ERROR @ 8044.872500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8044.872500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 40397278539835000457986623157101409975058752660390098881570073920424093979324 376
UVM_ERROR @ 23692.376500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 23692.376500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'
chip_sw_pwrmgr_sleep_power_glitch_reset 48972507543054477792852950331176932737244444353165895043667912722914212343329 313
UVM_ERROR @ 2808.089622 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2808.089622 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 22491492754487774615361813497480907855328261969229748876850786683885140686336 332
UVM_INFO @ 34491.877361 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *!
chip_sw_alert_test 8926437120801708319829905607064500232972980745534035792935039381266569348730 307
UVM_INFO @ 2734.797487 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 55590940334879787808459225574984900919462550616190070169180157340029823318768 308
UVM_INFO @ 2902.732510 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed!
chip_sw_alert_handler_lpg_sleep_mode_pings 44120228655860109017090137662167003807605783967223987685778815927984965619706 None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).
chip_tl_errors 25780976442559575316504774473767416589404860544611860875033198380979504050062 217
TL item was: req: (cip_tl_seq_item@31743) { a_addr: 'h10750 a_data: 'hbc2f48fd a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hd a_opcode: 'h4 a_user: 'h19580 d_param: 'h0 d_source: 'hd d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2613.847576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 104071728529726623930172000157683087599958046124033058568542300214651606799490 224
TL item was: req: (cip_tl_seq_item@32429) { a_addr: 'h10724 a_data: 'h8595eb78 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h8 a_opcode: 'h4 a_user: 'h18d85 d_param: 'h0 d_source: 'h8 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2319.400808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_clkmgr_jitter_frequency 27036234437698647524186134384758405936196718075242497756595827007222408256224 343
UVM_INFO @ 3823.340882 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']
chip_sw_pwrmgr_sleep_wake_5_bug 1981327561737510884424851296821768248505740374593434973092464988162437231164 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 79107266097234614697690923720243211709929715646785684560227179042626073419186 None
Another command (pid=442581) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=541562) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=414541) is running. Waiting for it to complete on the server (server_pid=236813)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 106012567289556944487981759819444725657164249048557959228179984686672948278705 None
---- STDERR ----
Another command (pid=541562) is running. Waiting for it to complete on the server (server_pid=236813)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 13407290699011313653332479865230082987191845437627750950662032531333392297738 None
Another command (pid=564219) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=568780) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=576567) is running. Waiting for it to complete on the server (server_pid=236813)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 111011733738993669297861715583896466118318729089008324657857475649562166494223 None
Another command (pid=576567) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=559890) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=565536) is running. Waiting for it to complete on the server (server_pid=236813)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 33438541788389754779170845363035101157390733632145917986366216278782263451510 None
Another command (pid=565536) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=456452) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=576346) is running. Waiting for it to complete on the server (server_pid=236813)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 33181983744305049231995746133208110097289927979433878387940053739892258336799 None
Another command (pid=600735) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=601941) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=590219) is running. Waiting for it to complete on the server (server_pid=236813)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 48645087050271277322505487040567932718956531342883346145413307026173061983636 None
---- STDERR ----
Another command (pid=443090) is running. Waiting for it to complete on the server (server_pid=236813)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 61952118880910657546307645966769247599817043590995181948093454611449517707982 None
Another command (pid=373526) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=447292) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=459310) is running. Waiting for it to complete on the server (server_pid=236813)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 62973409473961201961802419662436926218071597441674681176191182347619254351686 None
---- STDERR ----
Another command (pid=541562) is running. Waiting for it to complete on the server (server_pid=236813)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 20128658633984231405140832689216615415157872830470833560751070925811367265194 None
Another command (pid=414541) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=539946) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=373526) is running. Waiting for it to complete on the server (server_pid=236813)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 76119591474224808382459989133220006902251726055995389309929909706988925927319 None
Another command (pid=439014) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=435701) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=417621) is running. Waiting for it to complete on the server (server_pid=236813)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 109421880378796817855205749740325105665776795256826427581095500554449745904056 None
Another command (pid=421968) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=442581) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=541562) is running. Waiting for it to complete on the server (server_pid=236813)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 6274637779397274536316950667346017909223147037318582693367628167770910039281 None
Another command (pid=620397) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=637757) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=612869) is running. Waiting for it to complete on the server (server_pid=236813)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 62841752242018333083303051872112426582948638672674740630825993729533845512293 None
---- STDERR ----
Another command (pid=613936) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=605035) is running. Waiting for it to complete on the server (server_pid=236813)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 60677516949148052072274967028528669868754344203081513655658326861434444031574 None
Another command (pid=565536) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=572313) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=576346) is running. Waiting for it to complete on the server (server_pid=236813)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 103546148750217760730200816541762729401558753525475530230856288165676320991721 None
Another command (pid=607596) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=459658) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=613936) is running. Waiting for it to complete on the server (server_pid=236813)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 69490073522833460153238763688157102644594571456448256117542873794029170128188 None
Another command (pid=439014) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=427427) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=417621) is running. Waiting for it to complete on the server (server_pid=236813)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 28027020264690758015801379489265622515726305724737966729254105527181055914259 None
Another command (pid=443090) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=530063) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=457609) is running. Waiting for it to complete on the server (server_pid=236813)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 22858710891687444217955288404937050226495613715380967304606063160383147059609 None
Another command (pid=392618) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=377831) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=439014) is running. Waiting for it to complete on the server (server_pid=236813)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 30200649880518803417162135467317293333590587749672100782280589450565494872339 None
Another command (pid=530063) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=457609) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=434429) is running. Waiting for it to complete on the server (server_pid=236813)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 94542552132665502104929634074445195297702310446732259500479378430591753493760 None
Another command (pid=355815) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=392618) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=377831) is running. Waiting for it to complete on the server (server_pid=236813)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 70625091469035129405687483467590594850635751501387212107078773488645120033296 None
Another command (pid=539946) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=373526) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=551554) is running. Waiting for it to complete on the server (server_pid=236813)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 110297473501979202010851584295452630961720562580921108709623975480851287642704 None
Another command (pid=412321) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=443090) is running. Waiting for it to complete on the server (server_pid=236813)...
Another command (pid=457609) is running. Waiting for it to complete on the server (server_pid=236813)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: @@@:* = ErrorError
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 107629544773323421315627621562433106588020211062792294905447874785581681686140 317
UVM_INFO @ 6200.382827 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 81379529758612583177896665703226981172112236696394718108223206033964273109218 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 26572014710149094109551397843290634271835796951979259753537783064538145010801 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 102822717332153788873571026265936160051667849334552121698801323155927250854613 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 98669750081135875146242849821225875667161231775790562279225948117745856285645 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 110636553403302794002842167029400934022252877533055166319985820943671294948962 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 57885737943791488581053995943825891948679996049823462799635095453835332309307 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 71778583425900954120228046764873662145146581871811052813322249017797073436202 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 111222349718071939153438946215849653245169807777445244722281671578352055140430 235
UVM_INFO @ 5638.328727 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation.
chip_sw_rv_core_ibex_lockstep_glitch 37458974959108248243651011903350050880228782651155046284547004616294848058707 331
UVM_INFO @ 2786.242896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 45901650877275437990586348158583885532435338391704670388719497868694033395953 312
UVM_INFO @ 3434.476500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 96901171028488363401215270842961473944939682269059867484052494183596008618756 318
UVM_INFO @ 3591.273000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
chip_sw_ast_clk_rst_inputs 77471971831746134079575211610541823839857896463167048047390612057456067479937 327
UVM_INFO @ 12397.992597 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rom_e2e_shutdown_output_vseq.sv:23) [chip_sw_rom_e2e_shutdown_output_vseq] wait timeout occurred!
rom_e2e_shutdown_output 11362969833597336741317635900314191691421573584582860529800430547871107451563 339
UVM_INFO @ 31790.315439 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 105740354510494750465469759532466837765848998536575679543181932721822045324826 364
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 50248172977643423563494888807609068995074913539012082724452743152788752326462 326
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 89137004891091056132254582495599033404016697860514111577125721102328508989257 368
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 56512807209829364674863023067224990165154181207416960015731696228093456351033 326
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_prod 55610468563994656271921206774110619369548083432881012634065350577440245495141 368
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 46840656396231225143623833708714901903970300255297988623163285202266697058059 365
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 56242910078130378518842881437045624998485126631073322754475341460697275712077 364
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 99583414638148099067978868146480386812860146393372364085970001752015738964267 325
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 100357483696063476406769124555004978723000360264261760542299867234945944952228 327
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 11354429203227780599630767896768704769672246141279199773573800759397458312433 326
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 89576544564542138026340089875978188759177536498735019899816651719634785515163 325
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 47583855275202926526963652625334736127009963775440918916020459939908113497409 327
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 34744273821960510314613305051431808828018887650341748611906901259417207565395 326
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 112565553155228188151121437525562513513778442123803632035244584540858713353708 328
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 29440748801429930287756759255200038010520274609348389801972316153174112005255 328
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_no_meas 78516009408015622847129343796756725918774374761797016975917360189787419206578 319
UVM_INFO @ 16268.898480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
rom_keymgr_functest 22030667164882189974703384797373503917018857306908023799236023011729742721523 327
UVM_ERROR @ 4782.871332 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4782.871332 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---