Simulation Results: clkmgr

 
23/04/2026 15:30:30 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.67 %
  • code
  • 98.53 %
  • assert
  • 96.19 %
  • func
  • 86.28 %
  • line
  • 99.21 %
  • branch
  • 98.94 %
  • cond
  • 94.52 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.720s 16.395us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.820s 18.010us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.000s 37.272us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 6.110s 499.890us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.310s 261.026us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.470s 111.704us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 1.000s 37.272us 1 1 100.00
clkmgr_csr_aliasing 1.310s 261.026us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.840s 29.840us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.230s 59.372us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.960s 18.516us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.880s 55.733us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.720s 16.395us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 1.780s 498.043us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 2.410s 795.479us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 1.780s 498.043us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 13.910s 5240.302us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.750s 34.064us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.490s 63.237us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.490s 63.237us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.820s 18.010us 1 1 100.00
clkmgr_csr_rw 1.000s 37.272us 1 1 100.00
clkmgr_csr_aliasing 1.310s 261.026us 1 1 100.00
clkmgr_same_csr_outstanding 1.290s 228.603us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.820s 18.010us 1 1 100.00
clkmgr_csr_rw 1.000s 37.272us 1 1 100.00
clkmgr_csr_aliasing 1.310s 261.026us 1 1 100.00
clkmgr_same_csr_outstanding 1.290s 228.603us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
clkmgr_sec_cm 2.010s 378.415us 1 1 100.00
clkmgr_tl_intg_err 1.250s 67.460us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 2.110s 173.681us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 2.110s 173.681us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 2.110s 173.681us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 2.110s 173.681us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 5.290s 1591.178us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.250s 67.460us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 1.780s 498.043us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 2.410s 795.479us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 2.110s 173.681us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.810s 26.306us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.770s 54.559us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.960s 61.821us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.980s 49.172us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.880s 75.065us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.000s 37.272us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 2.010s 378.415us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.000s 37.272us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.000s 37.272us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 2.010s 378.415us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.280s 712.045us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 60.090s 22593.916us 1 1 100.00