Simulation Results: edn/edn0

 
23/04/2026 15:30:30 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.83 %
  • code
  • 84.14 %
  • assert
  • 96.96 %
  • func
  • 76.39 %
  • line
  • 98.42 %
  • branch
  • 94.28 %
  • cond
  • 86.30 %
  • toggle
  • 88.48 %
  • FSM
  • 53.23 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.810s 23.344us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.820s 16.256us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.880s 19.116us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.650s 665.114us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.070s 17.002us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.950s 22.170us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.880s 19.116us 1 1 100.00
edn_csr_aliasing 1.070s 17.002us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 3.500s 333.629us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 3.500s 333.629us 1 1 100.00
genbits 1 1 100.00
edn_genbits 3.500s 333.629us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.060s 28.369us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.120s 27.315us 1 1 100.00
errs 1 1 100.00
edn_err 1.060s 17.946us 1 1 100.00
disable 2 2 100.00
edn_disable 0.950s 14.416us 1 1 100.00
edn_disable_auto_req_mode 1.020s 51.303us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.570s 81.839us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.080s 21.007us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.960s 20.794us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.850s 39.915us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.850s 39.915us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.820s 16.256us 1 1 100.00
edn_csr_rw 0.880s 19.116us 1 1 100.00
edn_csr_aliasing 1.070s 17.002us 1 1 100.00
edn_same_csr_outstanding 0.990s 17.724us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.820s 16.256us 1 1 100.00
edn_csr_rw 0.880s 19.116us 1 1 100.00
edn_csr_aliasing 1.070s 17.002us 1 1 100.00
edn_same_csr_outstanding 0.990s 17.724us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.890s 1097.959us 1 1 100.00
edn_tl_intg_err 2.460s 132.267us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.790s 26.859us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.120s 27.315us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.890s 1097.959us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.890s 1097.959us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.890s 1097.959us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.890s 1097.959us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.120s 27.315us 1 1 100.00
edn_sec_cm 7.890s 1097.959us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.120s 27.315us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.460s 132.267us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 45.120s 2653.841us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 60257151765821985962806175303694791087302406279630214085352150488780555054064 208
UVM_INFO @ 2653841328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---