Simulation Results: edn/edn1

 
23/04/2026 15:30:30 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.87 %
  • code
  • 81.41 %
  • assert
  • 97.14 %
  • func
  • 76.05 %
  • line
  • 97.72 %
  • branch
  • 92.42 %
  • cond
  • 87.85 %
  • toggle
  • 84.72 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.840s 18.422us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.870s 51.400us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.760s 26.152us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.240s 61.721us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.140s 81.994us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.050s 19.713us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.760s 26.152us 1 1 100.00
edn_csr_aliasing 1.140s 81.994us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.870s 34.858us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.870s 34.858us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.870s 34.858us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.800s 24.567us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.080s 43.172us 1 1 100.00
errs 1 1 100.00
edn_err 1.070s 33.293us 1 1 100.00
disable 2 2 100.00
edn_disable 0.750s 19.162us 1 1 100.00
edn_disable_auto_req_mode 0.940s 65.917us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.120s 48.270us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.790s 22.004us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.920s 14.599us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.720s 123.253us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.720s 123.253us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.870s 51.400us 1 1 100.00
edn_csr_rw 0.760s 26.152us 1 1 100.00
edn_csr_aliasing 1.140s 81.994us 1 1 100.00
edn_same_csr_outstanding 1.000s 30.938us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.870s 51.400us 1 1 100.00
edn_csr_rw 0.760s 26.152us 1 1 100.00
edn_csr_aliasing 1.140s 81.994us 1 1 100.00
edn_same_csr_outstanding 1.000s 30.938us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.490s 1229.621us 1 1 100.00
edn_tl_intg_err 1.420s 72.336us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.930s 23.691us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.080s 43.172us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.490s 1229.621us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.490s 1229.621us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.490s 1229.621us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.490s 1229.621us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.080s 43.172us 1 1 100.00
edn_sec_cm 3.490s 1229.621us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.080s 43.172us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.420s 72.336us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 43.270s 3176.959us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 49725156150676576404150337051506822431762428561037619603146119446363387699077 244
UVM_INFO @ 3176958697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---