Simulation Results: flash_ctrl

 
23/04/2026 15:30:30 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.67 %
  • code
  • 94.15 %
  • assert
  • 96.76 %
  • func
  • 96.10 %
  • line
  • 95.96 %
  • branch
  • 97.19 %
  • cond
  • 93.71 %
  • toggle
  • 98.19 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
98.28%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 53.370s 96.566us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 14.180s 28.023us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 18.720s 102.496us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.810s 91.216us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 26.150s 6405.566us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 20.470s 456.793us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.020s 31.014us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.810s 91.216us 1 1 100.00
flash_ctrl_csr_aliasing 20.470s 456.793us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 7.330s 17.165us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.930s 20.747us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 17.390s 152.049us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 14.730s 88.007us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1268.410s 173585.398us 1 1 100.00
flash_ctrl_hw_rma_reset 552.630s 40129.920us 1 1 100.00
flash_ctrl_lcmgr_intg 6.700s 57.461us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1471.050s 372509.396us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 284.020s 15198.503us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 9.490s 219.144us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1978.390s 111246.794us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 69.480s 1414.787us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 13.850s 30.430us 1 1 100.00
flash_ctrl_rw_evict_all_en 15.700s 43.864us 1 1 100.00
flash_ctrl_re_evict 18.710s 116.445us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 51.380s 42.488us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 51.380s 42.488us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 88.640s 4704.928us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 11.370s 239.620us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 496.100s 161.608us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 389.270s 79317.626us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 321.120s 2369.973us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 675.140s 619.853us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.860s 41.443us 1 1 100.00
read_write_overflow 0 1 0.00
flash_ctrl_oversize_error 0.000s 0.000us 0 1 0.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 9.350s 162.737us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 10.050s 54.638us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 538.690s 579.011us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 48.020s 4153.581us 1 1 100.00
flash_ctrl_otp_reset 55.820s 465.224us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1268.410s 173585.398us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 134.420s 14748.328us 1 1 100.00
flash_ctrl_intr_wr 50.420s 9991.536us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 264.200s 46837.777us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 181.440s 205624.820us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 47.750s 1491.748us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 33.400s 1922.782us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 9.640s 65.343us 1 1 100.00
flash_ctrl_ro_derr 112.400s 4371.968us 1 1 100.00
flash_ctrl_rw_derr 220.790s 12191.829us 1 1 100.00
flash_ctrl_derr_detect 105.290s 1184.238us 1 1 100.00
flash_ctrl_integrity 610.670s 94718.399us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 8.710s 47.168us 1 1 100.00
flash_ctrl_ro_serr 77.590s 2437.357us 1 1 100.00
flash_ctrl_rw_serr 136.810s 6951.460us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 52.640s 2894.588us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 54.700s 785.409us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 139.890s 13082.653us 1 1 100.00
flash_ctrl_write_word_sweep 9.560s 78.555us 1 1 100.00
flash_ctrl_read_word_sweep 6.050s 47.201us 1 1 100.00
flash_ctrl_ro 80.690s 1393.555us 1 1 100.00
flash_ctrl_rw 451.440s 12390.480us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 29.830s 2296.593us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 618.820s 163841.547us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 82.990s 10019.540us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.690s 87.353us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 7.710s 37.132us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 7.590s 54.880us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 7.590s 54.880us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 18.720s 102.496us 1 1 100.00
flash_ctrl_csr_rw 8.810s 91.216us 1 1 100.00
flash_ctrl_csr_aliasing 20.470s 456.793us 1 1 100.00
flash_ctrl_same_csr_outstanding 7.100s 1004.907us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 18.720s 102.496us 1 1 100.00
flash_ctrl_csr_rw 8.810s 91.216us 1 1 100.00
flash_ctrl_csr_aliasing 20.470s 456.793us 1 1 100.00
flash_ctrl_same_csr_outstanding 7.100s 1004.907us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 18.340s 48.625us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 18.340s 48.625us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 18.340s 48.625us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 18.340s 48.625us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 34.680s 160.464us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1518.460s 5319.979us 1 1 100.00
flash_ctrl_tl_intg_err 179.750s 201.308us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 179.750s 201.308us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 179.750s 201.308us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 15.710s 63.424us 1 1 100.00
flash_ctrl_wr_intg 8.540s 47.056us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 53.370s 96.566us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 55.820s 465.224us 1 1 100.00
flash_ctrl_disable 9.350s 162.737us 1 1 100.00
flash_ctrl_sec_info_access 34.390s 546.231us 1 1 100.00
flash_ctrl_connect 10.050s 54.638us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.760s 22.740us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.810s 91.216us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 18.340s 48.625us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.810s 91.216us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 18.340s 48.625us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.810s 91.216us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 18.340s 48.625us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 9.350s 162.737us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 15.710s 63.424us 1 1 100.00
flash_ctrl_access_after_disable 7.700s 33.053us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 13.920s 30.078us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 9.350s 162.737us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 11.370s 239.620us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 451.440s 12390.480us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 136.810s 6951.460us 1 1 100.00
flash_ctrl_rw_derr 220.790s 12191.829us 1 1 100.00
flash_ctrl_integrity 610.670s 94718.399us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1268.410s 173585.398us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1518.460s 5319.979us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1518.460s 5319.979us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1518.460s 5319.979us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1518.460s 5319.979us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 14.650s 818.627us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 5.920s 23.935us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 10.540s 24.074us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1518.460s 5319.979us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1518.460s 5319.979us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1518.460s 5319.979us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 25.070s 148.872us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 259.580s 2876.513us 1 1 100.00

Error Messages

   Test seed line log context
Job killed!
flash_ctrl_oversize_error 51144417277840005378146198246151733265018633081462637589151841621488164044274 None