Simulation Results

Simulation Results: i2c

23/04/2026 15:30:30 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
86.76 %

code
81.85 %

assert
96.19 %

func
82.24 %

line
96.60 %

branch
92.69 %

cond
86.25 %

toggle
89.66 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		90.24%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	16.380s	1907.562us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	7.460s	3427.952us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.840s	45.611us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.790s	68.479us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	2.350s	631.073us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.230s	397.510us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.770s	65.669us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.790s	68.479us	1	1	100.00
	i2c_csr_aliasing	1.230s	397.510us	1	1	100.00

37/41 passed

90.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.920s	59.241us	0	1	0.00
host_stress_all				1	1	100.00
	i2c_host_stress_all	450.390s	14769.821us	1	1	100.00
host_maxperf				1	1	100.00
	i2c_host_perf	11.440s	1237.819us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.700s	21.168us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	81.900s	33621.899us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	115.180s	2430.976us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.120s	1854.499us	1	1	100.00
	i2c_host_fifo_fmt_empty	3.420s	1015.731us	1	1	100.00
	i2c_host_fifo_reset_rx	3.330s	535.595us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	66.260s	13354.711us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	8.930s	1400.262us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.690s	242.745us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.170s	1123.760us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	22.840s	6500.497us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.230s	2488.114us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	13.210s	458.101us	1	1	100.00
	i2c_target_intr_smoke	4.670s	979.689us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.790s	332.000us	1	1	100.00
	i2c_target_fifo_reset_tx	1.110s	131.949us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	217.700s	51121.928us	1	1	100.00
	i2c_target_stress_rd	13.210s	458.101us	1	1	100.00
	i2c_target_intr_stress_wr	31.530s	5738.079us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	5.690s	1426.446us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	3.240s	3959.030us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.210s	3346.763us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	4.700s	11072.419us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.840s	883.200us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.140s	304.168us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	11.440s	1237.819us	1	1	100.00
	i2c_host_perf_precise	1.650s	78.918us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	8.930s	1400.262us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	1.730s	92.336us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	1.880s	510.800us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.080s	471.352us	1	1	100.00
	i2c_target_nack_txstretch	1.350s	146.032us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	5.090s	7026.906us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.780s	1194.289us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.690s	16.931us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.770s	17.147us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.360s	148.090us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.360s	148.090us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.840s	45.611us	1	1	100.00
	i2c_csr_rw	0.790s	68.479us	1	1	100.00
	i2c_csr_aliasing	1.230s	397.510us	1	1	100.00
	i2c_same_csr_outstanding	1.110s	19.182us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.840s	45.611us	1	1	100.00
	i2c_csr_rw	0.790s	68.479us	1	1	100.00
	i2c_csr_aliasing	1.230s	397.510us	1	1	100.00
	i2c_same_csr_outstanding	1.110s	19.182us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.270s	291.815us	1	1	100.00
	i2c_sec_cm	1.300s	68.627us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.270s	291.815us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	5.670s	249.519us	1
target_error_intr				1
	i2c_target_unexp_stop	1.730s	397.699us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	1.190s	38.112us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
	i2c_host_error_intr	45159337949700058424905833550220210996478907878087163353521067557858751046422	104	UVM_INFO @ 59240722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	12385867237881585583676802893887677590869779493722572464346754858627603823040	85	UVM_INFO @ 38111768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	i2c_target_glitch	112196570708316733740153428707334123561226873571842612678148761174151452003097	84	UVM_INFO @ 1123759818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
	i2c_target_unexp_stop	95816678369682336374608223364515785933363620390028834258293362866216557468270	79	UVM_ERROR @ 397698882 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A UVM_INFO @ 397698882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
	i2c_target_hrst	71636897198119291450806637389640676470383189614309666968372112215377400963727	79	UVM_INFO @ 11072419082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	i2c_host_stress_all_with_rand_reset	83028799317961935274304817811103495057757193742133563151688959052131400239155	84	UVM_INFO @ 249518687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=, Comparison=CompareOpEq, exp_data=, call_count=3)
	i2c_host_mode_toggle	23332874461351092059662451704308570330860906829747749307725110797641371745346	79	UVM_INFO @ 242745253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---